MIPS: Optimize TLB handlers for Octeon CPUs · mariux64/linux@2c8c53e · GitHub

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MIPS: Optimize TLB handlers for Octeon CPUs

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Octeon can use scratch registers in the TLB handlers.  Octeon II can
use LDX instructions.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1904/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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David Daney authored and Ralf Baechle committed Jan 18, 2011

1 parent bb3d68c commit 2c8c53e