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Merge tag 'amd-drm-next-5.13-2021-03-23' of https://gitlab.freedeskto…
…p.org/agd5f/linux into drm-next amd-drm-next-5.13-2021-03-23: amdgpu: - Debugfs cleanup - Various cleanups and spelling fixes - Flexible array cleanups - Initial AMD Freesync HDMI - Display fixes - 10bpc dithering improvements - Display ASSR support - Clean up and unify powerplay and swsmu interfaces - Vangogh fixes - Add SMU gfx busy queues for RV/PCO - PCIE DPM fixes - S0ix fixes - GPU metrics data fixes - DCN secure display support - Backlight type override - Add initial support for Aldebaran - RAS fixes - Prime fixes for A+A systems - Reset fixes - Initial resource cursor support - Drop legacy IO BAR requirements - Various power fixes amdkfd: - MMU notifier fixes - APU fixes radeon: - Debugfs cleanups - Flexible array cleanups UAPI: - amdgpu: Add a new INFO ioctl interface to query video capabilities rather than hardcoding them in userspace. This allows us to provide fine grained asic capabilities (e.g., if a particular part is bandwidth limited, we can limit the capabilities). Proposed userspace: https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps - amdkfd: bump the driver version. There was a problem with reporting some RAS features on older versions of the driver. Proposed userspace: https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/commit/7cdd63475c36bb9f49bb960f90f9a8cdb7e80a21 Danvet: A bunch of conflicts all over, but it seems to compile ... I did put the call to dc_allow_idle_optimizations() on a single line since it looked a bit too jarring to be left alone. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210324040147.1990338-1-alexander.deucher@amd.com
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,54 @@ | ||
| /* | ||
| * Copyright 2020 Advanced Micro Devices, Inc. | ||
| * | ||
| * Permission is hereby granted, free of charge, to any person obtaining a | ||
| * copy of this software and associated documentation files (the "Software"), | ||
| * to deal in the Software without restriction, including without limitation | ||
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| * and/or sell copies of the Software, and to permit persons to whom the | ||
| * Software is furnished to do so, subject to the following conditions: | ||
| * | ||
| * The above copyright notice and this permission notice shall be included in | ||
| * all copies or substantial portions of the Software. | ||
| * | ||
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
| * OTHER DEALINGS IN THE SOFTWARE. | ||
| * | ||
| */ | ||
| #include "amdgpu.h" | ||
| #include "soc15.h" | ||
|
|
||
| #include "soc15_common.h" | ||
| #include "aldebaran_ip_offset.h" | ||
|
|
||
| int aldebaran_reg_base_init(struct amdgpu_device *adev) | ||
| { | ||
| /* HW has more IP blocks, only initialized the block needed by our driver */ | ||
| uint32_t i; | ||
| for (i = 0 ; i < MAX_INSTANCE ; ++i) { | ||
| adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); | ||
| adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); | ||
| adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); | ||
| adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); | ||
| adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); | ||
| adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); | ||
| adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); | ||
| adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); | ||
| adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); | ||
| adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); | ||
| adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); | ||
| adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i])); | ||
| adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i])); | ||
| adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i])); | ||
| adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); | ||
| adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); | ||
| adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i])); | ||
| adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); | ||
| } | ||
| return 0; | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,47 @@ | ||
| /* | ||
| * Copyright 2020 Advanced Micro Devices, Inc. | ||
| * | ||
| * Permission is hereby granted, free of charge, to any person obtaining a | ||
| * copy of this software and associated documentation files (the "Software"), | ||
| * to deal in the Software without restriction, including without limitation | ||
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| * and/or sell copies of the Software, and to permit persons to whom the | ||
| * Software is furnished to do so, subject to the following conditions: | ||
| * | ||
| * The above copyright notice and this permission notice shall be included in | ||
| * all copies or substantial portions of the Software. | ||
| * | ||
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
| * OTHER DEALINGS IN THE SOFTWARE. | ||
| */ | ||
| #include "amdgpu.h" | ||
| #include "amdgpu_amdkfd.h" | ||
| #include "amdgpu_amdkfd_arcturus.h" | ||
| #include "amdgpu_amdkfd_gfx_v9.h" | ||
|
|
||
| const struct kfd2kgd_calls aldebaran_kfd2kgd = { | ||
| .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, | ||
| .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, | ||
| .init_interrupts = kgd_gfx_v9_init_interrupts, | ||
| .hqd_load = kgd_gfx_v9_hqd_load, | ||
| .hiq_mqd_load = kgd_gfx_v9_hiq_mqd_load, | ||
| .hqd_sdma_load = kgd_arcturus_hqd_sdma_load, | ||
| .hqd_dump = kgd_gfx_v9_hqd_dump, | ||
| .hqd_sdma_dump = kgd_arcturus_hqd_sdma_dump, | ||
| .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied, | ||
| .hqd_sdma_is_occupied = kgd_arcturus_hqd_sdma_is_occupied, | ||
| .hqd_destroy = kgd_gfx_v9_hqd_destroy, | ||
| .hqd_sdma_destroy = kgd_arcturus_hqd_sdma_destroy, | ||
| .address_watch_disable = kgd_gfx_v9_address_watch_disable, | ||
| .address_watch_execute = kgd_gfx_v9_address_watch_execute, | ||
| .wave_control_execute = kgd_gfx_v9_wave_control_execute, | ||
| .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset, | ||
| .get_atc_vmid_pasid_mapping_info = | ||
| kgd_gfx_v9_get_atc_vmid_pasid_mapping_info, | ||
| .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base, | ||
| }; |
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