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drm/i915: Pass pipe_config to pch_enable() functions
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Using crtc->config directly is being removed in favor of passing a
pipe_config. Follow the trend and pass pipe_config to pch_enable()
functions.

v2: s/pipe_config/crtc_state/ (Ville)
  - constify crtc_state. (Ville)
  - take crtc from crtc_state. (Ville)
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170302125857.14665-4-ander.conselvan.de.oliveira@intel.com
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Ander Conselvan de Oliveira committed Mar 3, 2017
1 parent 0dcdc38 commit 2ce4227
Showing 1 changed file with 10 additions and 8 deletions.
18 changes: 10 additions & 8 deletions drivers/gpu/drm/i915/intel_display.c
Original file line number Diff line number Diff line change
Expand Up @@ -4455,8 +4455,9 @@ intel_trans_dp_port_sel(struct intel_crtc *crtc)
* - DP transcoding bits
* - transcoder
*/
static void ironlake_pch_enable(struct intel_crtc *crtc)
static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
int pipe = crtc->pipe;
Expand All @@ -4483,7 +4484,7 @@ static void ironlake_pch_enable(struct intel_crtc *crtc)
temp = I915_READ(PCH_DPLL_SEL);
temp |= TRANS_DPLL_ENABLE(pipe);
sel = TRANS_DPLLB_SEL(pipe);
if (crtc->config->shared_dpll ==
if (crtc_state->shared_dpll ==
intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
temp |= sel;
else
Expand All @@ -4508,9 +4509,9 @@ static void ironlake_pch_enable(struct intel_crtc *crtc)

/* For PCH DP, enable TRANS_DP_CTL */
if (HAS_PCH_CPT(dev_priv) &&
intel_crtc_has_dp_encoder(crtc->config)) {
intel_crtc_has_dp_encoder(crtc_state)) {
const struct drm_display_mode *adjusted_mode =
&crtc->config->base.adjusted_mode;
&crtc_state->base.adjusted_mode;
u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
i915_reg_t reg = TRANS_DP_CTL(pipe);
temp = I915_READ(reg);
Expand Down Expand Up @@ -4545,10 +4546,11 @@ static void ironlake_pch_enable(struct intel_crtc *crtc)
ironlake_enable_pch_transcoder(dev_priv, pipe);
}

static void lpt_pch_enable(struct intel_crtc *crtc)
static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);

Expand Down Expand Up @@ -5282,7 +5284,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_enable_pipe(intel_crtc);

if (intel_crtc->config->has_pch_encoder)
ironlake_pch_enable(intel_crtc);
ironlake_pch_enable(pipe_config);

assert_vblank_disabled(crtc);
drm_crtc_vblank_on(crtc);
Expand Down Expand Up @@ -5392,7 +5394,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_enable_pipe(intel_crtc);

if (intel_crtc->config->has_pch_encoder)
lpt_pch_enable(intel_crtc);
lpt_pch_enable(pipe_config);

if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
intel_ddi_set_vc_payload_alloc(crtc, true);
Expand Down

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