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dt-bindings: iio: dac: add docs for AXI DAC IP
This adds the bindings documentation for the Analog Devices AXI DAC IP core. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Nuno Sa <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20240419-iio-backend-axi-dac-v4-6-5ca45b4de294@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/iio/dac/adi,axi-dac.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Analog Devices AXI DAC IP core | ||
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maintainers: | ||
- Nuno Sa <nuno.sa@analog.com> | ||
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description: | | ||
Analog Devices Generic AXI DAC IP core for interfacing a DAC device | ||
with a high speed serial (JESD204B/C) or source synchronous parallel | ||
interface (LVDS/CMOS). | ||
Usually, some other interface type (i.e SPI) is used as a control | ||
interface for the actual DAC, while this IP core will interface | ||
to the data-lines of the DAC and handle the streaming of data from | ||
memory via DMA into the DAC. | ||
https://wiki.analog.com/resources/fpga/docs/axi_dac_ip | ||
properties: | ||
compatible: | ||
enum: | ||
- adi,axi-dac-9.1.b | ||
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reg: | ||
maxItems: 1 | ||
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dmas: | ||
maxItems: 1 | ||
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dma-names: | ||
items: | ||
- const: tx | ||
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clocks: | ||
maxItems: 1 | ||
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'#io-backend-cells': | ||
const: 0 | ||
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required: | ||
- compatible | ||
- dmas | ||
- reg | ||
- clocks | ||
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additionalProperties: false | ||
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examples: | ||
- | | ||
dac@44a00000 { | ||
compatible = "adi,axi-dac-9.1.b"; | ||
reg = <0x44a00000 0x10000>; | ||
dmas = <&tx_dma 0>; | ||
dma-names = "tx"; | ||
#io-backend-cells = <0>; | ||
clocks = <&axi_clk>; | ||
}; | ||
... |
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