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drm/i915/guc: Move guc_{send,recv}() to intel_uc.c
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guc_send(), guc_recv() and related functions were introduced in the
i915_guc_submission.c and their scope was limited only to that file.

Those are not submission specific though.
This patch moves moves them to intel_uc.c with intel_ prefix added.

v2: rename intel_guc_log_* functions and clean up intel_guc_send usages

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Winiarski <michal.winiarski@intel.com>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1480096777-12573-4-git-send-email-arkadiusz.hiler@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Arkadiusz Hiler authored and Chris Wilson committed Nov 25, 2016
1 parent a80bc45 commit 2d803c2
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Showing 4 changed files with 163 additions and 130 deletions.
3 changes: 2 additions & 1 deletion drivers/gpu/drm/i915/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,8 @@ i915-y += i915_cmd_parser.o \
intel_uncore.o

# general-purpose microcontroller (GuC) support
i915-y += intel_guc_loader.o \
i915-y += intel_uc.o \
intel_guc_loader.o \
i915_guc_submission.o

# autogenerated null render state
Expand Down
147 changes: 18 additions & 129 deletions drivers/gpu/drm/i915/i915_guc_submission.c
Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@
* Firmware writes a success/fail code back to the action register after
* processes the request. The kernel driver polls waiting for this update and
* then proceeds.
* See guc_send()
* See intel_guc_send()
*
* Doorbells:
* Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
Expand All @@ -65,141 +65,30 @@
*
*/

/*
* Read GuC command/status register (SOFT_SCRATCH_0)
* Return true if it contains a response rather than a command
*/
static inline bool guc_recv(struct drm_i915_private *dev_priv, u32 *status)
{
u32 val = I915_READ(SOFT_SCRATCH(0));
*status = val;
return INTEL_GUC_RECV_IS_RESPONSE(val);
}

static int guc_send(struct intel_guc *guc, u32 *data, u32 len)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
u32 status;
int i;
int ret;

if (WARN_ON(len < 1 || len > 15))
return -EINVAL;

mutex_lock(&guc->send_mutex);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

dev_priv->guc.action_count += 1;
dev_priv->guc.action_cmd = data[0];

for (i = 0; i < len; i++)
I915_WRITE(SOFT_SCRATCH(i), data[i]);

POSTING_READ(SOFT_SCRATCH(i - 1));

I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);

/*
* Fast commands should complete in less than 10us, so sample quickly
* up to that length of time, then switch to a slower sleep-wait loop.
* No INTEL_GUC_ACTION command should ever take longer than 10ms.
*/
ret = wait_for_us(guc_recv(dev_priv, &status), 10);
if (ret)
ret = wait_for(guc_recv(dev_priv, &status), 10);
if (status != INTEL_GUC_STATUS_SUCCESS) {
/*
* Either the GuC explicitly returned an error (which
* we convert to -EIO here) or no response at all was
* received within the timeout limit (-ETIMEDOUT)
*/
if (ret != -ETIMEDOUT)
ret = -EIO;

DRM_WARN("Action 0x%X failed; ret=%d status=0x%08X response=0x%08X\n",
data[0], ret, status, I915_READ(SOFT_SCRATCH(15)));

dev_priv->guc.action_fail += 1;
dev_priv->guc.action_err = ret;
}
dev_priv->guc.action_status = status;

intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
mutex_unlock(&guc->send_mutex);

return ret;
}

/*
* Tell the GuC to allocate or deallocate a specific doorbell
*/

static int guc_allocate_doorbell(struct intel_guc *guc,
struct i915_guc_client *client)
{
u32 data[2];
u32 action[] = {
INTEL_GUC_ACTION_ALLOCATE_DOORBELL,
client->ctx_index
};

data[0] = INTEL_GUC_ACTION_ALLOCATE_DOORBELL;
data[1] = client->ctx_index;

return guc_send(guc, data, 2);
return intel_guc_send(guc, action, ARRAY_SIZE(action));
}

static int guc_release_doorbell(struct intel_guc *guc,
struct i915_guc_client *client)
{
u32 data[2];

data[0] = INTEL_GUC_ACTION_DEALLOCATE_DOORBELL;
data[1] = client->ctx_index;

return guc_send(guc, data, 2);
}

static int guc_sample_forcewake(struct intel_guc *guc,
struct i915_guc_client *client)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
u32 data[2];

data[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
/* WaRsDisableCoarsePowerGating:skl,bxt */
if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
data[1] = 0;
else
/* bit 0 and 1 are for Render and Media domain separately */
data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;

return guc_send(guc, data, ARRAY_SIZE(data));
}

static int guc_logbuffer_flush_complete(struct intel_guc *guc)
{
u32 data[1];

data[0] = INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE;

return guc_send(guc, data, 1);
}

static int guc_force_logbuffer_flush(struct intel_guc *guc)
{
u32 data[2];

data[0] = INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH;
data[1] = 0;

return guc_send(guc, data, 2);
}

static int guc_logging_control(struct intel_guc *guc, u32 control_val)
{
u32 data[2];

data[0] = INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING;
data[1] = control_val;
u32 action[] = {
INTEL_GUC_ACTION_DEALLOCATE_DOORBELL,
client->ctx_index
};

return guc_send(guc, data, 2);
return intel_guc_send(guc, action, ARRAY_SIZE(action));
}

/*
Expand Down Expand Up @@ -297,7 +186,7 @@ select_doorbell_register(struct intel_guc *guc, uint32_t priority)
* Select, assign and relase doorbell cachelines
*
* These functions track which doorbell cachelines are in use.
* The data they manipulate is protected by the guc_send lock.
* The data they manipulate is protected by the intel_guc_send lock.
*/

static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
Expand Down Expand Up @@ -1525,7 +1414,7 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
}

guc->execbuf_client = client;
guc_sample_forcewake(guc, client);
intel_guc_sample_forcewake(guc);
guc_init_doorbell_hw(guc);

/* Take over from manual control of ELSP (execlists) */
Expand Down Expand Up @@ -1595,7 +1484,7 @@ int intel_guc_suspend(struct drm_device *dev)
/* first page is shared data with GuC */
data[2] = i915_ggtt_offset(ctx->engine[RCS].state);

return guc_send(guc, data, ARRAY_SIZE(data));
return intel_guc_send(guc, data, ARRAY_SIZE(data));
}


Expand Down Expand Up @@ -1623,7 +1512,7 @@ int intel_guc_resume(struct drm_device *dev)
/* first page is shared data with GuC */
data[2] = i915_ggtt_offset(ctx->engine[RCS].state);

return guc_send(guc, data, ARRAY_SIZE(data));
return intel_guc_send(guc, data, ARRAY_SIZE(data));
}

void i915_guc_capture_logs(struct drm_i915_private *dev_priv)
Expand All @@ -1634,7 +1523,7 @@ void i915_guc_capture_logs(struct drm_i915_private *dev_priv)
* time, so get/put should be really quick.
*/
intel_runtime_pm_get(dev_priv);
guc_logbuffer_flush_complete(&dev_priv->guc);
intel_guc_log_flush_complete(&dev_priv->guc);
intel_runtime_pm_put(dev_priv);
}

Expand All @@ -1652,7 +1541,7 @@ void i915_guc_flush_logs(struct drm_i915_private *dev_priv)
flush_work(&dev_priv->guc.log.flush_work);

/* Ask GuC to update the log buffer state */
guc_force_logbuffer_flush(&dev_priv->guc);
intel_guc_log_flush(&dev_priv->guc);

/* GuC would have updated log buffer by now, so capture it */
i915_guc_capture_logs(dev_priv);
Expand Down Expand Up @@ -1693,7 +1582,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
if (!log_param.logging_enabled && (i915.guc_log_level < 0))
return 0;

ret = guc_logging_control(&dev_priv->guc, log_param.value);
ret = intel_guc_log_control(&dev_priv->guc, log_param.value);
if (ret < 0) {
DRM_DEBUG_DRIVER("guc_logging_control action failed %d\n", ret);
return ret;
Expand Down
135 changes: 135 additions & 0 deletions drivers/gpu/drm/i915/intel_uc.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,135 @@
/*
* Copyright © 2016 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
*/

#include "i915_drv.h"
#include "intel_uc.h"

/*
* Read GuC command/status register (SOFT_SCRATCH_0)
* Return true if it contains a response rather than a command
*/
bool intel_guc_recv(struct drm_i915_private *dev_priv, u32 *status)
{
u32 val = I915_READ(SOFT_SCRATCH(0));
*status = val;
return INTEL_GUC_RECV_IS_RESPONSE(val);
}

int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
u32 status;
int i;
int ret;

if (WARN_ON(len < 1 || len > 15))
return -EINVAL;

mutex_lock(&guc->send_mutex);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

dev_priv->guc.action_count += 1;
dev_priv->guc.action_cmd = action[0];

for (i = 0; i < len; i++)
I915_WRITE(SOFT_SCRATCH(i), action[i]);

POSTING_READ(SOFT_SCRATCH(i - 1));

I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);

/*
* Fast commands should complete in less than 10us, so sample quickly
* up to that length of time, then switch to a slower sleep-wait loop.
* No inte_guc_send command should ever take longer than 10ms.
*/
ret = wait_for_us(intel_guc_recv(dev_priv, &status), 10);
if (ret)
ret = wait_for(intel_guc_recv(dev_priv, &status), 10);
if (status != INTEL_GUC_STATUS_SUCCESS) {
/*
* Either the GuC explicitly returned an error (which
* we convert to -EIO here) or no response at all was
* received within the timeout limit (-ETIMEDOUT)
*/
if (ret != -ETIMEDOUT)
ret = -EIO;

DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
" ret=%d status=0x%08X response=0x%08X\n",
action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));

dev_priv->guc.action_fail += 1;
dev_priv->guc.action_err = ret;
}
dev_priv->guc.action_status = status;

intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
mutex_unlock(&guc->send_mutex);

return ret;
}

int intel_guc_sample_forcewake(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
u32 action[2];

action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
/* WaRsDisableCoarsePowerGating:skl,bxt */
if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
action[1] = 0;
else
/* bit 0 and 1 are for Render and Media domain separately */
action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;

return intel_guc_send(guc, action, ARRAY_SIZE(action));
}

int intel_guc_log_flush_complete(struct intel_guc *guc)
{
u32 action[] = { INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE };

return intel_guc_send(guc, action, ARRAY_SIZE(action));
}

int intel_guc_log_flush(struct intel_guc *guc)
{
u32 action[] = {
INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH,
0
};

return intel_guc_send(guc, action, ARRAY_SIZE(action));
}

int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
{
u32 action[] = {
INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING,
control_val
};

return intel_guc_send(guc, action, ARRAY_SIZE(action));
}
8 changes: 8 additions & 0 deletions drivers/gpu/drm/i915/intel_uc.h
Original file line number Diff line number Diff line change
Expand Up @@ -168,6 +168,14 @@ struct intel_guc {
struct mutex send_mutex;
};

/* intel_uc.c */
bool intel_guc_recv(struct drm_i915_private *dev_priv, u32 *status);
int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len);
int intel_guc_sample_forcewake(struct intel_guc *guc);
int intel_guc_log_flush_complete(struct intel_guc *guc);
int intel_guc_log_flush(struct intel_guc *guc);
int intel_guc_log_control(struct intel_guc *guc, u32 control_val);

/* intel_guc_loader.c */
extern void intel_guc_init(struct drm_device *dev);
extern int intel_guc_setup(struct drm_device *dev);
Expand Down

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