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r8169: remove fiddling with the PCIe max read request size
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The attempt to improve performance by changing the PCIe max read request
size was added in the vendor driver more than 10 years back and copied
to r8169 driver. In the vendor driver this has been removed long ago.
Obviously it had no effect, also in my tests I didn't see any
difference. Typically the max payload size is less than 512 bytes
anyway, and the PCI core takes care that the maximum supported value
is set. So let's remove fiddling with PCIe max read request size from
r8169 too.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
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Heiner Kallweit authored and Jakub Kicinski committed Oct 22, 2019
1 parent bd71a35 commit 2df49d3
Showing 1 changed file with 4 additions and 36 deletions.
40 changes: 4 additions & 36 deletions drivers/net/ethernet/realtek/r8169_main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -741,12 +741,6 @@ static void rtl_unlock_config_regs(struct rtl8169_private *tp)
RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
}

static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
{
pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_READRQ, force);
}

static bool rtl_is_8125(struct rtl8169_private *tp)
{
return tp->mac_version >= RTL_GIGA_MAC_VER_60;
Expand Down Expand Up @@ -4032,14 +4026,12 @@ static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
{
RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
}

static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
{
RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
}

static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
Expand All @@ -4057,27 +4049,25 @@ static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
RTL_W8(tp, MaxTxPacketSize, 0x3f);
RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
}

static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
{
RTL_W8(tp, MaxTxPacketSize, 0x0c);
RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
}

static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
{
rtl_tx_performance_tweak(tp,
PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_NOSNOOP_EN);
}

static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
{
rtl_tx_performance_tweak(tp,
PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_NOSNOOP_EN);
}

static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
Expand Down Expand Up @@ -4550,18 +4540,12 @@ static void rtl_hw_start_8168d(struct rtl8169_private *tp)
rtl_set_def_aspm_entry_latency(tp);

rtl_disable_clock_request(tp);

if (tp->dev->mtu <= ETH_DATA_LEN)
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
}

static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
{
rtl_set_def_aspm_entry_latency(tp);

if (tp->dev->mtu <= ETH_DATA_LEN)
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);

rtl_disable_clock_request(tp);
}

Expand All @@ -4576,8 +4560,6 @@ static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)

rtl_set_def_aspm_entry_latency(tp);

rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);

rtl_ephy_init(tp, e_info_8168d_4);

rtl_enable_clock_request(tp);
Expand Down Expand Up @@ -4652,8 +4634,6 @@ static void rtl_hw_start_8168f(struct rtl8169_private *tp)
{
rtl_set_def_aspm_entry_latency(tp);

rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);

rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
Expand Down Expand Up @@ -4716,8 +4696,6 @@ static void rtl_hw_start_8168g(struct rtl8169_private *tp)

rtl_set_def_aspm_entry_latency(tp);

rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);

rtl_reset_packet_filter(tp);
rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);

Expand Down Expand Up @@ -4954,8 +4932,6 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)

rtl_set_def_aspm_entry_latency(tp);

rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);

rtl_reset_packet_filter(tp);

rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
Expand Down Expand Up @@ -5013,8 +4989,6 @@ static void rtl_hw_start_8168ep(struct rtl8169_private *tp)

rtl_set_def_aspm_entry_latency(tp);

rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);

rtl_reset_packet_filter(tp);

rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
Expand Down Expand Up @@ -5117,8 +5091,6 @@ static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)

RTL_W8(tp, DBG_REG, FIX_NAK_1);

rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);

RTL_W8(tp, Config1,
LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
Expand All @@ -5134,8 +5106,6 @@ static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
{
rtl_set_def_aspm_entry_latency(tp);

rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);

RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
}
Expand Down Expand Up @@ -5196,8 +5166,6 @@ static void rtl_hw_start_8402(struct rtl8169_private *tp)

rtl_ephy_init(tp, e_info_8402);

rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);

rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
rtl_reset_packet_filter(tp);
rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
Expand Down

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