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Merge branch 'dsa-microchip-phylink-mac-config'
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Arun Ramadoss says:

====================
net: dsa: microchip: add support for phylink mac config and link up

This patch series add support common phylink mac config and link up for the ksz
series switches. At present, ksz8795 and ksz9477 doesn't implement the phylink
mac config and link up. It configures the mac interface in the port setup hook.
ksz8830 series switch does not mac link configuration. For lan937x switches, in
the part support patch series has support only for MII and RMII configuration.
Some group of switches have some register address and bit fields common and
others are different. So, this patch aims to have common phylink implementation
which configures the register based on the chip id.

Changes in v2
- combined the modification of duplex, tx_pause and rx_pause into single
  function.

Changes in v1
- Squash the reading rgmii value from dt to patch which apply the rgmii value
- Created the new function ksz_port_set_xmii_speed
- Seperated the namespace values for xmii_ctrl_0 and xmii_ctrl_1 register
- Applied the rgmii delay value based on the rx/tx-internal-delay-ps
====================

Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller committed Jul 27, 2022
2 parents 060468f + f3d890f commit 2f0f6b1
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Showing 9 changed files with 431 additions and 355 deletions.
40 changes: 0 additions & 40 deletions drivers/net/dsa/microchip/ksz8795.c
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Original file line number Diff line number Diff line change
Expand Up @@ -26,11 +26,6 @@
#include "ksz8795_reg.h"
#include "ksz8.h"

static bool ksz_is_ksz88x3(struct ksz_device *dev)
{
return dev->chip_id == 0x8830;
}

static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
{
regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
Expand Down Expand Up @@ -1116,7 +1111,6 @@ void ksz8_port_mirror_del(struct ksz_device *dev, int port,
static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
{
struct ksz_port *p = &dev->ports[port];
u8 data8;

if (!p->interface && dev->compat_interface) {
dev_warn(dev->dev,
Expand All @@ -1125,40 +1119,6 @@ static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
port);
p->interface = dev->compat_interface;
}

/* Configure MII interface for proper network communication. */
ksz_read8(dev, REG_PORT_5_CTRL_6, &data8);
data8 &= ~PORT_INTERFACE_TYPE;
data8 &= ~PORT_GMII_1GPS_MODE;
switch (p->interface) {
case PHY_INTERFACE_MODE_MII:
p->phydev.speed = SPEED_100;
break;
case PHY_INTERFACE_MODE_RMII:
data8 |= PORT_INTERFACE_RMII;
p->phydev.speed = SPEED_100;
break;
case PHY_INTERFACE_MODE_GMII:
data8 |= PORT_GMII_1GPS_MODE;
data8 |= PORT_INTERFACE_GMII;
p->phydev.speed = SPEED_1000;
break;
default:
data8 &= ~PORT_RGMII_ID_IN_ENABLE;
data8 &= ~PORT_RGMII_ID_OUT_ENABLE;
if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
data8 |= PORT_RGMII_ID_IN_ENABLE;
if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
data8 |= PORT_RGMII_ID_OUT_ENABLE;
data8 |= PORT_GMII_1GPS_MODE;
data8 |= PORT_INTERFACE_RGMII;
p->phydev.speed = SPEED_1000;
break;
}
ksz_write8(dev, REG_PORT_5_CTRL_6, data8);
p->phydev.duplex = 1;
}

void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
Expand Down
8 changes: 0 additions & 8 deletions drivers/net/dsa/microchip/ksz8795_reg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -170,15 +170,7 @@
#define REG_PORT_5_CTRL_6 0x56

#define PORT_MII_INTERNAL_CLOCK BIT(7)
#define PORT_GMII_1GPS_MODE BIT(6)
#define PORT_RGMII_ID_IN_ENABLE BIT(4)
#define PORT_RGMII_ID_OUT_ENABLE BIT(3)
#define PORT_GMII_MAC_MODE BIT(2)
#define PORT_INTERFACE_TYPE 0x3
#define PORT_INTERFACE_MII 0
#define PORT_INTERFACE_RMII 1
#define PORT_INTERFACE_GMII 2
#define PORT_INTERFACE_RGMII 3

#define REG_PORT_1_CTRL_7 0x17
#define REG_PORT_2_CTRL_7 0x27
Expand Down
183 changes: 6 additions & 177 deletions drivers/net/dsa/microchip/ksz9477.c
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Original file line number Diff line number Diff line change
Expand Up @@ -19,11 +19,6 @@
#include "ksz_common.h"
#include "ksz9477.h"

/* Used with variable features to indicate capabilities. */
#define GBIT_SUPPORT BIT(0)
#define NEW_XMII BIT(1)
#define IS_9893 BIT(2)

static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
{
regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
Expand Down Expand Up @@ -866,142 +861,18 @@ void ksz9477_port_mirror_del(struct ksz_device *dev, int port,
PORT_MIRROR_SNIFFER, false);
}

static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data)
{
bool gbit;

if (dev->features & NEW_XMII)
gbit = !(data & PORT_MII_NOT_1GBIT);
else
gbit = !!(data & PORT_MII_1000MBIT_S1);
return gbit;
}

static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data)
{
if (dev->features & NEW_XMII) {
if (gbit)
*data &= ~PORT_MII_NOT_1GBIT;
else
*data |= PORT_MII_NOT_1GBIT;
} else {
if (gbit)
*data |= PORT_MII_1000MBIT_S1;
else
*data &= ~PORT_MII_1000MBIT_S1;
}
}

static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
{
int mode;

if (dev->features & NEW_XMII) {
switch (data & PORT_MII_SEL_M) {
case PORT_MII_SEL:
mode = 0;
break;
case PORT_RMII_SEL:
mode = 1;
break;
case PORT_GMII_SEL:
mode = 2;
break;
default:
mode = 3;
}
} else {
switch (data & PORT_MII_SEL_M) {
case PORT_MII_SEL_S1:
mode = 0;
break;
case PORT_RMII_SEL_S1:
mode = 1;
break;
case PORT_GMII_SEL_S1:
mode = 2;
break;
default:
mode = 3;
}
}
return mode;
}

static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)
{
u8 xmii;

if (dev->features & NEW_XMII) {
switch (mode) {
case 0:
xmii = PORT_MII_SEL;
break;
case 1:
xmii = PORT_RMII_SEL;
break;
case 2:
xmii = PORT_GMII_SEL;
break;
default:
xmii = PORT_RGMII_SEL;
break;
}
} else {
switch (mode) {
case 0:
xmii = PORT_MII_SEL_S1;
break;
case 1:
xmii = PORT_RMII_SEL_S1;
break;
case 2:
xmii = PORT_GMII_SEL_S1;
break;
default:
xmii = PORT_RGMII_SEL_S1;
break;
}
}
*data &= ~PORT_MII_SEL_M;
*data |= xmii;
}

static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
{
phy_interface_t interface;
bool gbit;
int mode;
u8 data8;

if (port < dev->phy_port_cnt)
return PHY_INTERFACE_MODE_NA;
ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
gbit = ksz9477_get_gbit(dev, data8);
mode = ksz9477_get_xmii(dev, data8);
switch (mode) {
case 2:
interface = PHY_INTERFACE_MODE_GMII;
if (gbit)
break;
fallthrough;
case 0:
interface = PHY_INTERFACE_MODE_MII;
break;
case 1:
interface = PHY_INTERFACE_MODE_RMII;
break;
default:
interface = PHY_INTERFACE_MODE_RGMII;
if (data8 & PORT_RGMII_ID_EG_ENABLE)
interface = PHY_INTERFACE_MODE_RGMII_TXID;
if (data8 & PORT_RGMII_ID_IG_ENABLE) {
interface = PHY_INTERFACE_MODE_RGMII_RXID;
if (data8 & PORT_RGMII_ID_EG_ENABLE)
interface = PHY_INTERFACE_MODE_RGMII_ID;
}
break;
}

gbit = ksz_get_gbit(dev, port);

interface = ksz_get_xmii(dev, port, gbit);

return interface;
}

Expand Down Expand Up @@ -1073,10 +944,9 @@ void ksz9477_get_caps(struct ksz_device *dev, int port,

void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
{
struct ksz_port *p = &dev->ports[port];
struct dsa_switch *ds = dev->ds;
u8 data8, member;
u16 data16;
u8 member;

/* enable tag tail for host port */
if (cpu_port)
Expand Down Expand Up @@ -1116,44 +986,6 @@ void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
true);

/* configure MAC to 1G & RGMII mode */
ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
switch (p->interface) {
case PHY_INTERFACE_MODE_MII:
ksz9477_set_xmii(dev, 0, &data8);
ksz9477_set_gbit(dev, false, &data8);
p->phydev.speed = SPEED_100;
break;
case PHY_INTERFACE_MODE_RMII:
ksz9477_set_xmii(dev, 1, &data8);
ksz9477_set_gbit(dev, false, &data8);
p->phydev.speed = SPEED_100;
break;
case PHY_INTERFACE_MODE_GMII:
ksz9477_set_xmii(dev, 2, &data8);
ksz9477_set_gbit(dev, true, &data8);
p->phydev.speed = SPEED_1000;
break;
default:
ksz9477_set_xmii(dev, 3, &data8);
ksz9477_set_gbit(dev, true, &data8);
data8 &= ~PORT_RGMII_ID_IG_ENABLE;
data8 &= ~PORT_RGMII_ID_EG_ENABLE;
if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
data8 |= PORT_RGMII_ID_IG_ENABLE;
if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
data8 |= PORT_RGMII_ID_EG_ENABLE;
/* On KSZ9893, disable RGMII in-band status support */
if (dev->features & IS_9893)
data8 &= ~PORT_MII_MAC_MODE;
p->phydev.speed = SPEED_1000;
break;
}
ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
p->phydev.duplex = 1;
}

if (cpu_port)
Expand Down Expand Up @@ -1341,9 +1173,6 @@ int ksz9477_switch_init(struct ksz_device *dev)
dev->features &= ~GBIT_SUPPORT;
dev->phy_port_cnt = 2;
} else {
/* Chip uses new XMII register definitions. */
dev->features |= NEW_XMII;

/* Chip does not support gigabit. */
if (!(data8 & SW_GIGABIT_ABLE))
dev->features &= ~GBIT_SUPPORT;
Expand Down
24 changes: 0 additions & 24 deletions drivers/net/dsa/microchip/ksz9477_reg.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1175,35 +1175,11 @@
#define PORT_LINK_STATUS_FAIL BIT(0)

/* 3 - xMII */
#define REG_PORT_XMII_CTRL_0 0x0300

#define PORT_SGMII_SEL BIT(7)
#define PORT_MII_FULL_DUPLEX BIT(6)
#define PORT_MII_100MBIT BIT(4)
#define PORT_GRXC_ENABLE BIT(0)

#define REG_PORT_XMII_CTRL_1 0x0301

#define PORT_RMII_CLK_SEL BIT(7)
/* S1 */
#define PORT_MII_1000MBIT_S1 BIT(6)
/* S2 */
#define PORT_MII_NOT_1GBIT BIT(6)
#define PORT_MII_SEL_EDGE BIT(5)
#define PORT_RGMII_ID_IG_ENABLE BIT(4)
#define PORT_RGMII_ID_EG_ENABLE BIT(3)
#define PORT_MII_MAC_MODE BIT(2)
#define PORT_MII_SEL_M 0x3
/* S1 */
#define PORT_MII_SEL_S1 0x0
#define PORT_RMII_SEL_S1 0x1
#define PORT_GMII_SEL_S1 0x2
#define PORT_RGMII_SEL_S1 0x3
/* S2 */
#define PORT_RGMII_SEL 0x0
#define PORT_RMII_SEL 0x1
#define PORT_GMII_SEL 0x2
#define PORT_MII_SEL 0x3

/* 4 - MAC */
#define REG_PORT_MAC_CTRL_0 0x0400
Expand Down
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