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MIPS: Add core files for MIPS SEAD-3 development platform.
More information about the SEAD-3 platform can be found at <http://www.mips.com/products/development-kits/mips-sead-3/> on MTI's site. Currently, the M14K family of cores is what the SEAD-3 is utilised with. Signed-off-by: Douglas Leung <douglas@mips.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Steven J. Hill <sjhill@mips.com>
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/* | ||
* This file is subject to the terms and conditions of the GNU General Public | ||
* License. See the file "COPYING" in the main directory of this archive | ||
* for more details. | ||
* | ||
* Copyright (C) 2003, 2004 Chris Dearman | ||
* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) | ||
*/ | ||
#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H | ||
#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H | ||
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/* | ||
* CPU feature overrides for MIPS boards | ||
*/ | ||
#ifdef CONFIG_CPU_MIPS32 | ||
#define cpu_has_tlb 1 | ||
#define cpu_has_4kex 1 | ||
#define cpu_has_4k_cache 1 | ||
/* #define cpu_has_fpu ? */ | ||
/* #define cpu_has_32fpr ? */ | ||
#define cpu_has_counter 1 | ||
/* #define cpu_has_watch ? */ | ||
#define cpu_has_divec 1 | ||
#define cpu_has_vce 0 | ||
/* #define cpu_has_cache_cdex_p ? */ | ||
/* #define cpu_has_cache_cdex_s ? */ | ||
/* #define cpu_has_prefetch ? */ | ||
#define cpu_has_mcheck 1 | ||
/* #define cpu_has_ejtag ? */ | ||
#ifdef CONFIG_CPU_HAS_LLSC | ||
#define cpu_has_llsc 1 | ||
#else | ||
#define cpu_has_llsc 0 | ||
#endif | ||
/* #define cpu_has_vtag_icache ? */ | ||
/* #define cpu_has_dc_aliases ? */ | ||
/* #define cpu_has_ic_fills_f_dc ? */ | ||
#define cpu_has_nofpuex 0 | ||
/* #define cpu_has_64bits ? */ | ||
/* #define cpu_has_64bit_zero_reg ? */ | ||
/* #define cpu_has_inclusive_pcaches ? */ | ||
#define cpu_icache_snoops_remote_store 1 | ||
#endif | ||
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#ifdef CONFIG_CPU_MIPS64 | ||
#define cpu_has_tlb 1 | ||
#define cpu_has_4kex 1 | ||
#define cpu_has_4k_cache 1 | ||
/* #define cpu_has_fpu ? */ | ||
/* #define cpu_has_32fpr ? */ | ||
#define cpu_has_counter 1 | ||
/* #define cpu_has_watch ? */ | ||
#define cpu_has_divec 1 | ||
#define cpu_has_vce 0 | ||
/* #define cpu_has_cache_cdex_p ? */ | ||
/* #define cpu_has_cache_cdex_s ? */ | ||
/* #define cpu_has_prefetch ? */ | ||
#define cpu_has_mcheck 1 | ||
/* #define cpu_has_ejtag ? */ | ||
#define cpu_has_llsc 1 | ||
/* #define cpu_has_vtag_icache ? */ | ||
/* #define cpu_has_dc_aliases ? */ | ||
/* #define cpu_has_ic_fills_f_dc ? */ | ||
#define cpu_has_nofpuex 0 | ||
/* #define cpu_has_64bits ? */ | ||
/* #define cpu_has_64bit_zero_reg ? */ | ||
/* #define cpu_has_inclusive_pcaches ? */ | ||
#define cpu_icache_snoops_remote_store 1 | ||
#endif | ||
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#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ |
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#ifndef __ASM_MACH_MIPS_IRQ_H | ||
#define __ASM_MACH_MIPS_IRQ_H | ||
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#define NR_IRQS 256 | ||
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#include_next <irq.h> | ||
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#endif /* __ASM_MACH_MIPS_IRQ_H */ |
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/* | ||
* This file is subject to the terms and conditions of the GNU General Public | ||
* License. See the file "COPYING" in the main directory of this archive | ||
* for more details. | ||
* | ||
* Chris Dearman (chris@mips.com) | ||
* Copyright (C) 2007 Mips Technologies, Inc. | ||
*/ | ||
#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H | ||
#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H | ||
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.macro kernel_entry_setup | ||
#ifdef CONFIG_MIPS_MT_SMTC | ||
mfc0 t0, CP0_CONFIG | ||
bgez t0, 9f | ||
mfc0 t0, CP0_CONFIG, 1 | ||
bgez t0, 9f | ||
mfc0 t0, CP0_CONFIG, 2 | ||
bgez t0, 9f | ||
mfc0 t0, CP0_CONFIG, 3 | ||
and t0, 1<<2 | ||
bnez t0, 0f | ||
9 : | ||
/* Assume we came from YAMON... */ | ||
PTR_LA v0, 0x9fc00534 /* YAMON print */ | ||
lw v0, (v0) | ||
move a0, zero | ||
PTR_LA a1, nonmt_processor | ||
jal v0 | ||
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PTR_LA v0, 0x9fc00520 /* YAMON exit */ | ||
lw v0, (v0) | ||
li a0, 1 | ||
jal v0 | ||
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1 : b 1b | ||
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__INITDATA | ||
nonmt_processor : | ||
.asciz "SMTC kernel requires the MT ASE to run\n" | ||
__FINIT | ||
0 : | ||
#endif | ||
.endm | ||
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/* | ||
* Do SMP slave processor setup necessary before we can safely execute C code. | ||
*/ | ||
.macro smp_slave_setup | ||
.endm | ||
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#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ |
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/* | ||
* This file is subject to the terms and conditions of the GNU General Public | ||
* License. See the file "COPYING" in the main directory of this archive | ||
* for more details. | ||
* | ||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
*/ | ||
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H | ||
#define __ASM_MIPS_MACH_MIPS_WAR_H | ||
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#define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
#define R4600_V1_HIT_CACHEOP_WAR 0 | ||
#define R4600_V2_HIT_CACHEOP_WAR 0 | ||
#define R5432_CP0_INTERRUPT_WAR 0 | ||
#define BCM1250_M3_WAR 0 | ||
#define SIBYTE_1956_WAR 0 | ||
#define MIPS4K_ICACHE_REFILL_WAR 1 | ||
#define MIPS_CACHE_SYNC_WAR 1 | ||
#define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
#define RM9000_CDEX_SMP_WAR 0 | ||
#define ICACHE_REFILLS_WORKAROUND_WAR 1 | ||
#define R10000_LLSC_WAR 0 | ||
#define MIPS34K_MISSED_ITLB_WAR 0 | ||
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#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ |
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/* | ||
* This file is subject to the terms and conditions of the GNU General Public | ||
* License. See the file "COPYING" in the main directory of this archive | ||
* for more details. | ||
* | ||
* Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. | ||
* Douglas Leung <douglas@mips.com> | ||
* Steven J. Hill <sjhill@mips.com> | ||
*/ | ||
#ifndef _MIPS_SEAD3INT_H | ||
#define _MIPS_SEAD3INT_H | ||
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/* SEAD-3 GIC address space definitions. */ | ||
#define GIC_BASE_ADDR 0x1b1c0000 | ||
#define GIC_ADDRSPACE_SZ (128 * 1024) | ||
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#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0) | ||
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#endif /* !(_MIPS_SEAD3INT_H) */ |
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# | ||
# Carsten Langgaard, carstenl@mips.com | ||
# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. | ||
# | ||
# Copyright (C) 2008 Wind River Systems, Inc. | ||
# written by Ralf Baechle <ralf@linux-mips.org> | ||
# | ||
obj-y := sead3-lcd.o sead3-cmdline.o \ | ||
sead3-display.o sead3-init.o sead3-int.o \ | ||
sead3-mtd.o sead3-net.o \ | ||
sead3-memory.o sead3-platform.o \ | ||
sead3-reset.o sead3-setup.o sead3-time.o | ||
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obj-y += sead3-i2c-dev.o sead3-i2c.o \ | ||
sead3-pic32-i2c-drv.o sead3-pic32-bus.o \ | ||
leds-sead3.o sead3-leds.o | ||
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obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o | ||
obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o |
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# | ||
# MIPS SEAD-3 board | ||
# | ||
platform-$(CONFIG_MIPS_SEAD3) += mti-sead3/ | ||
cflags-$(CONFIG_MIPS_SEAD3) += -I$(srctree)/arch/mips/include/asm/mach-sead3 | ||
load-$(CONFIG_MIPS_SEAD3) += 0xffffffff80100000 | ||
all-$(CONFIG_MIPS_SEAD3) := $(COMPRESSION_FNAME).srec |
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/* | ||
* This file is subject to the terms and conditions of the GNU General Public | ||
* License. See the file "COPYING" in the main directory of this archive | ||
* for more details. | ||
* | ||
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | ||
*/ | ||
#include <linux/kernel.h> | ||
#include <linux/module.h> | ||
#include <linux/init.h> | ||
#include <linux/platform_device.h> | ||
#include <linux/leds.h> | ||
#include <linux/err.h> | ||
#include <linux/io.h> | ||
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#define DRVNAME "sead3-led" | ||
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static struct platform_device *pdev; | ||
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static void sead3_pled_set(struct led_classdev *led_cdev, | ||
enum led_brightness value) | ||
{ | ||
pr_debug("sead3_pled_set\n"); | ||
writel(value, (void __iomem *)0xBF000210); /* FIXME */ | ||
} | ||
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static void sead3_fled_set(struct led_classdev *led_cdev, | ||
enum led_brightness value) | ||
{ | ||
pr_debug("sead3_fled_set\n"); | ||
writel(value, (void __iomem *)0xBF000218); /* FIXME */ | ||
} | ||
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static struct led_classdev sead3_pled = { | ||
.name = "sead3::pled", | ||
.brightness_set = sead3_pled_set, | ||
}; | ||
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static struct led_classdev sead3_fled = { | ||
.name = "sead3::fled", | ||
.brightness_set = sead3_fled_set, | ||
}; | ||
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#ifdef CONFIG_PM | ||
static int sead3_led_suspend(struct platform_device *dev, | ||
pm_message_t state) | ||
{ | ||
led_classdev_suspend(&sead3_pled); | ||
led_classdev_suspend(&sead3_fled); | ||
return 0; | ||
} | ||
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static int sead3_led_resume(struct platform_device *dev) | ||
{ | ||
led_classdev_resume(&sead3_pled); | ||
led_classdev_resume(&sead3_fled); | ||
return 0; | ||
} | ||
#else | ||
#define sead3_led_suspend NULL | ||
#define sead3_led_resume NULL | ||
#endif | ||
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static int sead3_led_probe(struct platform_device *pdev) | ||
{ | ||
int ret; | ||
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ret = led_classdev_register(&pdev->dev, &sead3_pled); | ||
if (ret < 0) | ||
return ret; | ||
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ret = led_classdev_register(&pdev->dev, &sead3_fled); | ||
if (ret < 0) | ||
led_classdev_unregister(&sead3_pled); | ||
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return ret; | ||
} | ||
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static int sead3_led_remove(struct platform_device *pdev) | ||
{ | ||
led_classdev_unregister(&sead3_pled); | ||
led_classdev_unregister(&sead3_fled); | ||
return 0; | ||
} | ||
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static struct platform_driver sead3_led_driver = { | ||
.probe = sead3_led_probe, | ||
.remove = sead3_led_remove, | ||
.suspend = sead3_led_suspend, | ||
.resume = sead3_led_resume, | ||
.driver = { | ||
.name = DRVNAME, | ||
.owner = THIS_MODULE, | ||
}, | ||
}; | ||
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static int __init sead3_led_init(void) | ||
{ | ||
int ret; | ||
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ret = platform_driver_register(&sead3_led_driver); | ||
if (ret < 0) | ||
goto out; | ||
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pdev = platform_device_register_simple(DRVNAME, -1, NULL, 0); | ||
if (IS_ERR(pdev)) { | ||
ret = PTR_ERR(pdev); | ||
platform_driver_unregister(&sead3_led_driver); | ||
goto out; | ||
} | ||
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out: | ||
return ret; | ||
} | ||
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static void __exit sead3_led_exit(void) | ||
{ | ||
platform_device_unregister(pdev); | ||
platform_driver_unregister(&sead3_led_driver); | ||
} | ||
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module_init(sead3_led_init); | ||
module_exit(sead3_led_exit); | ||
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MODULE_AUTHOR("Kristian Kielhofner <kris@krisk.org>"); | ||
MODULE_DESCRIPTION("SEAD3 LED driver"); | ||
MODULE_LICENSE("GPL"); | ||
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/* | ||
* This file is subject to the terms and conditions of the GNU General Public | ||
* License. See the file "COPYING" in the main directory of this archive | ||
* for more details. | ||
* | ||
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | ||
*/ | ||
#include <linux/init.h> | ||
#include <linux/string.h> | ||
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#include <asm/bootinfo.h> | ||
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extern int prom_argc; | ||
extern int *_prom_argv; | ||
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/* | ||
* YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. | ||
* This macro take care of sign extension. | ||
*/ | ||
#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) | ||
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char * __init prom_getcmdline(void) | ||
{ | ||
return &(arcs_cmdline[0]); | ||
} | ||
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void __init prom_init_cmdline(void) | ||
{ | ||
char *cp; | ||
int actr; | ||
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actr = 1; /* Always ignore argv[0] */ | ||
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cp = &(arcs_cmdline[0]); | ||
while (actr < prom_argc) { | ||
strcpy(cp, prom_argv(actr)); | ||
cp += strlen(prom_argv(actr)); | ||
*cp++ = ' '; | ||
actr++; | ||
} | ||
if (cp != &(arcs_cmdline[0])) { | ||
/* get rid of trailing space */ | ||
--cp; | ||
*cp = '\0'; | ||
} | ||
} |
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