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Merge tag 'pm-5.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kerne…
…l/git/rafael/linux-pm Pull more power management updates from Rafael Wysocki: "These are mostly ARM cpufreq driver updates, including one new MediaTek driver that has just passed all of the reviews, with the addition of a revert of a recent intel_pstate commit, some core cpufreq changes and a DT-related update of the operating performance points (OPP) support code. Specifics: - Add new cpufreq driver for the MediaTek MT6779 platform called mediatek-hw along with corresponding DT bindings (Hector.Yuan). - Add DCVS interrupt support to the qcom-cpufreq-hw driver (Thara Gopinath). - Make the qcom-cpufreq-hw driver set the dvfs_possible_from_any_cpu policy flag (Taniya Das). - Blocklist more Qualcomm platforms in cpufreq-dt-platdev (Bjorn Andersson). - Make the vexpress cpufreq driver set the CPUFREQ_IS_COOLING_DEV flag (Viresh Kumar). - Add new cpufreq driver callback to allow drivers to register with the Energy Model in a consistent way and make several drivers use it (Viresh Kumar). - Change the remaining users of the .ready() cpufreq driver callback to move the code from it elsewhere and drop it from the cpufreq core (Viresh Kumar). - Revert recent intel_pstate change adding HWP guaranteed performance change notification support to it that led to problems, because the notification in question is triggered prematurely on some systems (Rafael Wysocki). - Convert the OPP DT bindings to DT schema and clean them up while at it (Rob Herring)" * tag 'pm-5.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (23 commits) Revert "cpufreq: intel_pstate: Process HWP Guaranteed change notification" cpufreq: mediatek-hw: Add support for CPUFREQ HW cpufreq: Add of_perf_domain_get_sharing_cpumask dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW cpufreq: Remove ready() callback cpufreq: sh: Remove sh_cpufreq_cpu_ready() cpufreq: acpi: Remove acpi_cpufreq_cpu_ready() cpufreq: qcom-hw: Set dvfs_possible_from_any_cpu cpufreq driver flag cpufreq: blocklist more Qualcomm platforms in cpufreq-dt-platdev cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support cpufreq: scmi: Use .register_em() to register with energy model cpufreq: vexpress: Use .register_em() to register with energy model cpufreq: scpi: Use .register_em() to register with energy model dt-bindings: opp: Convert to DT schema dt-bindings: Clean-up OPP binding node names in examples ARM: dts: omap: Drop references to opp.txt cpufreq: qcom-cpufreq-hw: Use .register_em() to register with energy model cpufreq: omap: Use .register_em() to register with energy model cpufreq: mediatek: Use .register_em() to register with energy model cpufreq: imx6q: Use .register_em() to register with energy model ...
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Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: MediaTek's CPUFREQ Bindings | ||
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maintainers: | ||
- Hector Yuan <hector.yuan@mediatek.com> | ||
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description: | ||
CPUFREQ HW is a hardware engine used by MediaTek SoCs to | ||
manage frequency in hardware. It is capable of controlling | ||
frequency for multiple clusters. | ||
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properties: | ||
compatible: | ||
const: mediatek,cpufreq-hw | ||
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reg: | ||
minItems: 1 | ||
maxItems: 2 | ||
description: | ||
Addresses and sizes for the memory of the HW bases in | ||
each frequency domain. Each entry corresponds to | ||
a register bank for each frequency domain present. | ||
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"#performance-domain-cells": | ||
description: | ||
Number of cells in a performance domain specifier. | ||
Set const to 1 here for nodes providing multiple | ||
performance domains. | ||
const: 1 | ||
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required: | ||
- compatible | ||
- reg | ||
- "#performance-domain-cells" | ||
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additionalProperties: false | ||
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examples: | ||
- | | ||
cpus { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
cpu0: cpu@0 { | ||
device_type = "cpu"; | ||
compatible = "arm,cortex-a55"; | ||
enable-method = "psci"; | ||
performance-domains = <&performance 0>; | ||
reg = <0x000>; | ||
}; | ||
}; | ||
/* ... */ | ||
soc { | ||
#address-cells = <2>; | ||
#size-cells = <2>; | ||
performance: performance-controller@11bc00 { | ||
compatible = "mediatek,cpufreq-hw"; | ||
reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; | ||
#performance-domain-cells = <1>; | ||
}; | ||
}; |
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/opp/opp-v1.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Generic OPP (Operating Performance Points) v1 Bindings | ||
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maintainers: | ||
- Viresh Kumar <viresh.kumar@linaro.org> | ||
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description: |+ | ||
Devices work at voltage-current-frequency combinations and some implementations | ||
have the liberty of choosing these. These combinations are called Operating | ||
Performance Points aka OPPs. This document defines bindings for these OPPs | ||
applicable across wide range of devices. For illustration purpose, this document | ||
uses CPU as a device. | ||
This binding only supports voltage-frequency pairs. | ||
select: true | ||
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properties: | ||
operating-points: | ||
$ref: /schemas/types.yaml#/definitions/uint32-matrix | ||
items: | ||
items: | ||
- description: Frequency in kHz | ||
- description: Voltage for OPP in uV | ||
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additionalProperties: true | ||
examples: | ||
- | | ||
cpus { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
cpu@0 { | ||
compatible = "arm,cortex-a9"; | ||
device_type = "cpu"; | ||
reg = <0>; | ||
next-level-cache = <&L2>; | ||
operating-points = | ||
/* kHz uV */ | ||
<792000 1100000>, | ||
<396000 950000>, | ||
<198000 850000>; | ||
}; | ||
}; | ||
... |
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