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Merge tag 'pm-5.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kerne…
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…l/git/rafael/linux-pm

Pull more power management updates from Rafael Wysocki:
 "These are mostly ARM cpufreq driver updates, including one new
  MediaTek driver that has just passed all of the reviews, with the
  addition of a revert of a recent intel_pstate commit, some core
  cpufreq changes and a DT-related update of the operating performance
  points (OPP) support code.

  Specifics:

   - Add new cpufreq driver for the MediaTek MT6779 platform called
     mediatek-hw along with corresponding DT bindings (Hector.Yuan).

   - Add DCVS interrupt support to the qcom-cpufreq-hw driver (Thara
     Gopinath).

   - Make the qcom-cpufreq-hw driver set the dvfs_possible_from_any_cpu
     policy flag (Taniya Das).

   - Blocklist more Qualcomm platforms in cpufreq-dt-platdev (Bjorn
     Andersson).

   - Make the vexpress cpufreq driver set the CPUFREQ_IS_COOLING_DEV
     flag (Viresh Kumar).

   - Add new cpufreq driver callback to allow drivers to register with
     the Energy Model in a consistent way and make several drivers use
     it (Viresh Kumar).

   - Change the remaining users of the .ready() cpufreq driver callback
     to move the code from it elsewhere and drop it from the cpufreq
     core (Viresh Kumar).

   - Revert recent intel_pstate change adding HWP guaranteed performance
     change notification support to it that led to problems, because the
     notification in question is triggered prematurely on some systems
     (Rafael Wysocki).

   - Convert the OPP DT bindings to DT schema and clean them up while at
     it (Rob Herring)"

* tag 'pm-5.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (23 commits)
  Revert "cpufreq: intel_pstate: Process HWP Guaranteed change notification"
  cpufreq: mediatek-hw: Add support for CPUFREQ HW
  cpufreq: Add of_perf_domain_get_sharing_cpumask
  dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW
  cpufreq: Remove ready() callback
  cpufreq: sh: Remove sh_cpufreq_cpu_ready()
  cpufreq: acpi: Remove acpi_cpufreq_cpu_ready()
  cpufreq: qcom-hw: Set dvfs_possible_from_any_cpu cpufreq driver flag
  cpufreq: blocklist more Qualcomm platforms in cpufreq-dt-platdev
  cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support
  cpufreq: scmi: Use .register_em() to register with energy model
  cpufreq: vexpress: Use .register_em() to register with energy model
  cpufreq: scpi: Use .register_em() to register with energy model
  dt-bindings: opp: Convert to DT schema
  dt-bindings: Clean-up OPP binding node names in examples
  ARM: dts: omap: Drop references to opp.txt
  cpufreq: qcom-cpufreq-hw: Use .register_em() to register with energy model
  cpufreq: omap: Use .register_em() to register with energy model
  cpufreq: mediatek: Use .register_em() to register with energy model
  cpufreq: imx6q: Use .register_em() to register with energy model
  ...
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Linus Torvalds committed Sep 8, 2021
2 parents 9c56661 + f76c87e commit 30f3490
Showing 39 changed files with 1,441 additions and 767 deletions.
3 changes: 0 additions & 3 deletions Documentation/cpu-freq/cpu-drivers.rst
Original file line number Diff line number Diff line change
@@ -75,9 +75,6 @@ And optionally
.resume - A pointer to a per-policy resume function which is called
with interrupts disabled and _before_ the governor is started again.

.ready - A pointer to a per-policy ready function which is called after
the policy is fully initialized.

.attr - A pointer to a NULL-terminated list of "struct freq_attr" which
allow to export values to sysfs.

2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt
Original file line number Diff line number Diff line change
@@ -11,7 +11,7 @@ Required properties:
- None

Optional properties:
- operating-points: Refer to Documentation/devicetree/bindings/opp/opp.txt for
- operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for
details. OPPs *must* be supplied either via DT, i.e. this property, or
populated at runtime.
- clock-latency: Specify the possible maximum transition latency for clock,
70 changes: 70 additions & 0 deletions Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek's CPUFREQ Bindings

maintainers:
- Hector Yuan <hector.yuan@mediatek.com>

description:
CPUFREQ HW is a hardware engine used by MediaTek SoCs to
manage frequency in hardware. It is capable of controlling
frequency for multiple clusters.

properties:
compatible:
const: mediatek,cpufreq-hw

reg:
minItems: 1
maxItems: 2
description:
Addresses and sizes for the memory of the HW bases in
each frequency domain. Each entry corresponds to
a register bank for each frequency domain present.

"#performance-domain-cells":
description:
Number of cells in a performance domain specifier.
Set const to 1 here for nodes providing multiple
performance domains.
const: 1

required:
- compatible
- reg
- "#performance-domain-cells"

additionalProperties: false

examples:
- |
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
performance-domains = <&performance 0>;
reg = <0x000>;
};
};
/* ... */
soc {
#address-cells = <2>;
#size-cells = <2>;
performance: performance-controller@11bc00 {
compatible = "mediatek,cpufreq-hw";
reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
#performance-domain-cells = <1>;
};
};
Original file line number Diff line number Diff line change
@@ -10,7 +10,7 @@ Required properties:
transition and not stable yet.
Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
generic clock consumer properties.
- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
for detail.
- proc-supply: Regulator for Vproc of CPU cluster.

6 changes: 2 additions & 4 deletions Documentation/devicetree/bindings/cpufreq/cpufreq-st.txt
Original file line number Diff line number Diff line change
@@ -6,16 +6,14 @@ from the SoC, then supplies the OPP framework with 'prop' and 'supported
hardware' information respectively. The framework is then able to read
the DT and operate in the usual way.

For more information about the expected DT format [See: ../opp/opp.txt].

Frequency Scaling only
----------------------

No vendor specific driver required for this.

Located in CPU's node:

- operating-points : [See: ../power/opp.txt]
- operating-points : [See: ../power/opp-v1.yaml]

Example [safe]
--------------
@@ -37,7 +35,7 @@ This requires the ST CPUFreq driver to supply 'process' and 'version' info.

Located in CPU's node:

- operating-points-v2 : [See ../power/opp.txt]
- operating-points-v2 : [See ../power/opp-v2.yaml]

Example [unsafe]
----------------
Original file line number Diff line number Diff line change
@@ -4,7 +4,7 @@ Binding for NVIDIA Tegra20 CPUFreq
Required properties:
- clocks: Must contain an entry for the CPU clock.
See ../clocks/clock-bindings.txt for details.
- operating-points-v2: See ../bindings/opp/opp.txt for details.
- operating-points-v2: See ../bindings/opp/opp-v2.yaml for details.
- #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details.

For each opp entry in 'operating-points-v2' table:
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
Original file line number Diff line number Diff line change
@@ -8,7 +8,7 @@ Required properties:
- clocks: Phandles for clock specified in "clock-names" property
- clock-names : The name of clock used by the DFI, must be
"pclk_ddr_mon";
- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt
- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
for details.
- center-supply: DMC supply node.
- status: Marks the node enabled/disabled.
Original file line number Diff line number Diff line change
@@ -137,7 +137,7 @@ examples:
resets = <&reset 0>, <&reset 1>;
};
gpu_opp_table: opp_table0 {
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-533000000 {
Original file line number Diff line number Diff line change
@@ -160,7 +160,7 @@ examples:
#cooling-cells = <2>;
};
gpu_opp_table: opp_table0 {
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-533000000 {
Original file line number Diff line number Diff line change
@@ -81,10 +81,10 @@ examples:
noc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-133M {
opp-133333333 {
opp-hz = /bits/ 64 <133333333>;
};
opp-800M {
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
};
};
Original file line number Diff line number Diff line change
@@ -18,6 +18,9 @@ description: |
sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
provide the OPP framework with required information.
allOf:
- $ref: opp-v2-base.yaml#

properties:
compatible:
const: allwinner,sun50i-h6-operating-points
@@ -43,6 +46,7 @@ patternProperties:

properties:
opp-hz: true
clock-latency-ns: true

patternProperties:
"opp-microvolt-.*": true
51 changes: 51 additions & 0 deletions Documentation/devicetree/bindings/opp/opp-v1.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/opp/opp-v1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic OPP (Operating Performance Points) v1 Bindings

maintainers:
- Viresh Kumar <viresh.kumar@linaro.org>

description: |+
Devices work at voltage-current-frequency combinations and some implementations
have the liberty of choosing these. These combinations are called Operating
Performance Points aka OPPs. This document defines bindings for these OPPs
applicable across wide range of devices. For illustration purpose, this document
uses CPU as a device.
This binding only supports voltage-frequency pairs.
select: true

properties:
operating-points:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: Frequency in kHz
- description: Voltage for OPP in uV


additionalProperties: true
examples:
- |
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points =
/* kHz uV */
<792000 1100000>,
<396000 950000>,
<198000 850000>;
};
};
...
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