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bnx2x: Minor code improvements
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Minor code improvements
Small changes to make the code a little bit more efficient and mostly
more readable:
- Using unified macros for EMAC_RD/WR which looks like normal REG_RD/WR
- Removing the NIG_WR since it did nothing and was only confusing
- On bnx2x_panic_dump, print only the used parts of the rings
- define parameters only on the branch they are needed and not at the
  beginning of the function
- using NETIF_MSG_INTR and not private BNX2X_MSG_SP for debug prints

Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Eilon Greenstein authored and David S. Miller committed Aug 13, 2008
1 parent f0e53a8 commit 3196a88
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Showing 3 changed files with 72 additions and 78 deletions.
23 changes: 10 additions & 13 deletions drivers/net/bnx2x.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -121,16 +121,7 @@
#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)

#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
#define NIG_WR(reg, val) REG_WR(bp, reg, val)
#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val)
#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)


#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)

#define for_each_nondefault_queue(bp, var) \
for (var = 1; var < bp->num_queues; var++)
#define is_multi(bp) (bp->num_queues > 1)
#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)


/* fast path */
Expand Down Expand Up @@ -815,9 +806,6 @@ struct bnx2x {
#define BP_FUNC(bp) (bp->func)
#define BP_E1HVN(bp) (bp->func >> 1)
#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
/* assorted E1HVN */
#define IS_E1HMF(bp) (bp->e1hmf != 0)
#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)

int pm_cap;
int pcie_cap;
Expand All @@ -842,6 +830,7 @@ struct bnx2x {
u32 mf_config;
u16 e1hov;
u8 e1hmf;
#define IS_E1HMF(bp) (bp->e1hmf != 0)

u8 wol;

Expand Down Expand Up @@ -872,6 +861,7 @@ struct bnx2x {
#define BNX2X_STATE_ERROR 0xf000

int num_queues;
#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)

u32 rx_mode;
#define BNX2X_RX_MODE_NONE 0
Expand Down Expand Up @@ -922,6 +912,13 @@ struct bnx2x {
};


#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)

#define for_each_nondefault_queue(bp, var) \
for (var = 1; var < bp->num_queues; var++)
#define is_multi(bp) (bp->num_queues > 1)


void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
u32 len32);
Expand Down
57 changes: 29 additions & 28 deletions drivers/net/bnx2x_link.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@

/********************************************************/
#define SUPPORT_CL73 0 /* Currently no */
#define ETH_HLEN 14
#define ETH_HLEN 14
#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
#define ETH_MIN_PACKET_SIZE 60
#define ETH_MAX_PACKET_SIZE 1500
Expand All @@ -40,7 +40,7 @@
#define BMAC_CONTROL_RX_ENABLE 2

/***********************************************************/
/* Shortcut definitions */
/* Shortcut definitions */
/***********************************************************/

#define NIG_STATUS_XGXS0_LINK10G \
Expand Down Expand Up @@ -79,12 +79,12 @@

#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
#define AUTONEG_PARALLEL \
#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
#define AUTONEG_PARALLEL \
SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
#define AUTONEG_SGMII_FIBER_AUTODET \
#define AUTONEG_SGMII_FIBER_AUTODET \
SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY

#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
Expand Down Expand Up @@ -201,30 +201,29 @@ static void bnx2x_emac_init(struct link_params *params,
/* init emac - use read-modify-write */
/* self clear reset */
val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));

timeout = 200;
do
{
do {
val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
if (!timeout) {
DP(NETIF_MSG_LINK, "EMAC timeout!\n");
return;
}
timeout--;
}while (val & EMAC_MODE_RESET);
} while (val & EMAC_MODE_RESET);

/* Set mac address */
val = ((params->mac_addr[0] << 8) |
params->mac_addr[1]);
EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val);
EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);

val = ((params->mac_addr[2] << 24) |
(params->mac_addr[3] << 16) |
(params->mac_addr[4] << 8) |
params->mac_addr[5]);
EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val);
EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
}

static u8 bnx2x_emac_enable(struct link_params *params,
Expand Down Expand Up @@ -285,7 +284,7 @@ static u8 bnx2x_emac_enable(struct link_params *params,
if (CHIP_REV_IS_SLOW(bp)) {
/* config GMII mode */
val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
EMAC_WR(EMAC_REG_EMAC_MODE,
EMAC_WR(bp, EMAC_REG_EMAC_MODE,
(val | EMAC_MODE_PORT_GMII));
} else { /* ASIC */
/* pause enable/disable */
Expand All @@ -309,18 +308,18 @@ static u8 bnx2x_emac_enable(struct link_params *params,
/* KEEP_VLAN_TAG, promiscuous */
val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
EMAC_WR(EMAC_REG_EMAC_RX_MODE, val);
EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);

/* Set Loopback */
val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
if (lb)
val |= 0x810;
else
val &= ~0x810;
EMAC_WR(EMAC_REG_EMAC_MODE, val);
EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);

/* enable emac for jumbo packets */
EMAC_WR(EMAC_REG_EMAC_RX_MTU_SIZE,
EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
(EMAC_RX_MTU_SIZE_JUMBO_ENA |
(ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));

Expand Down Expand Up @@ -646,7 +645,7 @@ static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
NIG_REG_INGRESS_BMAC0_MEM;
u32 wb_data[2];
u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);

/* Only if the bmac is out of reset */
if (REG_RD(bp, MISC_REG_RESET_REG_2) &
Expand Down Expand Up @@ -1036,7 +1035,7 @@ static void bnx2x_set_swap_lanes(struct link_params *params)
}

static void bnx2x_set_parallel_detection(struct link_params *params,
u8 phy_flags)
u8 phy_flags)
{
struct bnx2x *bp = params->bp;
u16 control2;
Expand Down Expand Up @@ -1489,8 +1488,8 @@ static u8 bnx2x_ext_phy_resove_fc(struct link_params *params,
{
struct bnx2x *bp = params->bp;
u8 ext_phy_addr;
u16 ld_pause; /* local */
u16 lp_pause; /* link partner */
u16 ld_pause; /* local */
u16 lp_pause; /* link partner */
u16 an_complete; /* AN complete */
u16 pause_result;
u8 ret = 0;
Expand Down Expand Up @@ -1565,8 +1564,8 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
u32 gp_status)
{
struct bnx2x *bp = params->bp;
u16 ld_pause; /* local driver */
u16 lp_pause; /* link partner */
u16 ld_pause; /* local driver */
u16 lp_pause; /* link partner */
u16 pause_result;

vars->flow_ctrl = FLOW_CTRL_NONE;
Expand Down Expand Up @@ -1611,6 +1610,7 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
u32 gp_status)
{
struct bnx2x *bp = params->bp;

u8 rc = 0;
vars->link_status = 0;

Expand Down Expand Up @@ -3303,7 +3303,7 @@ static void bnx2x_link_int_enable(struct link_params *params)
* link management
*/
static void bnx2x_link_int_ack(struct link_params *params,
struct link_vars *vars, u16 is_10g)
struct link_vars *vars, u8 is_10g)
{
struct bnx2x *bp = params->bp;
u8 port = params->port;
Expand Down Expand Up @@ -3781,7 +3781,7 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
SHARED_HW_CFG_LED_MAC1);

tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
EMAC_WR(EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
break;

case LED_MODE_OPER:
Expand All @@ -3794,7 +3794,7 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
port*4, 1);
tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
EMAC_WR(EMAC_REG_EMAC_LED,
EMAC_WR(bp, EMAC_REG_EMAC_LED,
(tmp & (~EMAC_LED_OVERRIDE)));

if (!CHIP_IS_E1H(bp) &&
Expand Down Expand Up @@ -3917,7 +3917,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
struct bnx2x *bp = params->bp;

u32 val;
DP(NETIF_MSG_LINK, "Phy Initialization started\n");
DP(NETIF_MSG_LINK, "Phy Initialization started \n");
DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n",
params->req_line_speed, params->req_flow_ctrl);
vars->link_status = 0;
Expand All @@ -3933,6 +3933,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
else
vars->phy_flags = PHY_XGXS_FLAG;


/* disable attentions */
bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
(NIG_MASK_XGXS0_LINK_STATUS |
Expand Down Expand Up @@ -4542,7 +4543,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
size = MAX_APP_SIZE+HEADER_SIZE;
}
DP(NETIF_MSG_LINK, "File version is %c%c\n", data[0x14e], data[0x14f]);
DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]);
DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]);
/* Put the DSP in download mode by setting FLASH_CFG[2] to 1
and issuing a reset.*/

Expand Down Expand Up @@ -4824,7 +4825,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
MDIO_PMA_REG_7101_VER2,
&image_revision2);

if (data[0x14e] != (image_revision2&0xFF) ||
if (data[0x14e] != (image_revision2&0xFF) ||
data[0x14f] != ((image_revision2&0xFF00)>>8) ||
data[0x150] != (image_revision1&0xFF) ||
data[0x151] != ((image_revision1&0xFF00)>>8)) {
Expand Down
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