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drm/amdkfd: replace kgd_dev in various kfd2kgd funcs
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Modified definitions:

- program_sh_mem_settings
- set_pasid_vmid_mapping
- init_interrupts
- address_watch_disable
- address_watch_execute
- wave_control_execute
- address_watch_get_offset
- get_atc_vmid_pasid_mapping_info
- set_scratch_backing_va
- set_vm_context_page_table_base
- read_vmid_from_vmfault_reg
- get_cu_occupancy
- program_trap_handler_settings

Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Graham Sider authored and Alex Deucher committed Nov 17, 2021
1 parent 420185f commit 3356c38
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Showing 12 changed files with 106 additions and 174 deletions.
33 changes: 11 additions & 22 deletions drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -80,14 +80,12 @@ static void release_queue(struct amdgpu_device *adev)
unlock_srbm(adev);
}

static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,
uint32_t sh_mem_config,
uint32_t sh_mem_ape1_base,
uint32_t sh_mem_ape1_limit,
uint32_t sh_mem_bases)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

lock_srbm(adev, 0, 0, 0, vmid);

WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
Expand All @@ -97,11 +95,9 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
unlock_srbm(adev);
}

static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, u32 pasid,
static int kgd_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,
unsigned int vmid)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

/*
* We have to assume that there is no outstanding mapping.
* The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
Expand Down Expand Up @@ -144,9 +140,8 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, u32 pasid,
* but still works
*/

static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
static int kgd_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
uint32_t mec;
uint32_t pipe;

Expand Down Expand Up @@ -669,11 +664,10 @@ static int kgd_hqd_sdma_destroy(struct amdgpu_device *adev, void *mqd,
return 0;
}

static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
uint8_t vmid, uint16_t *p_pasid)
{
uint32_t value;
struct amdgpu_device *adev = (struct amdgpu_device *) kgd;

value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
+ vmid);
Expand All @@ -682,12 +676,12 @@ static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
}

static int kgd_address_watch_disable(struct kgd_dev *kgd)
static int kgd_address_watch_disable(struct amdgpu_device *adev)
{
return 0;
}

static int kgd_address_watch_execute(struct kgd_dev *kgd,
static int kgd_address_watch_execute(struct amdgpu_device *adev,
unsigned int watch_point_id,
uint32_t cntl_val,
uint32_t addr_hi,
Expand All @@ -696,11 +690,10 @@ static int kgd_address_watch_execute(struct kgd_dev *kgd,
return 0;
}

static int kgd_wave_control_execute(struct kgd_dev *kgd,
static int kgd_wave_control_execute(struct amdgpu_device *adev,
uint32_t gfx_index_val,
uint32_t sq_cmd)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
uint32_t data = 0;

mutex_lock(&adev->grbm_idx_mutex);
Expand All @@ -721,18 +714,16 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd,
return 0;
}

static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
static uint32_t kgd_address_watch_get_offset(struct amdgpu_device *adev,
unsigned int watch_point_id,
unsigned int reg_offset)
{
return 0;
}

static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
uint64_t page_table_base)
static void set_vm_context_page_table_base(struct amdgpu_device *adev,
uint32_t vmid, uint64_t page_table_base)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
pr_err("trying to set page table base for wrong VMID %u\n",
vmid);
Expand All @@ -743,11 +734,9 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);
}

static void program_trap_handler_settings(struct kgd_dev *kgd,
static void program_trap_handler_settings(struct amdgpu_device *adev,
uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

lock_srbm(adev, 0, 0, 0, vmid);

/*
Expand Down
49 changes: 16 additions & 33 deletions drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -79,14 +79,12 @@ static void release_queue(struct amdgpu_device *adev)
unlock_srbm(adev);
}

static void program_sh_mem_settings_v10_3(struct kgd_dev *kgd, uint32_t vmid,
static void program_sh_mem_settings_v10_3(struct amdgpu_device *adev, uint32_t vmid,
uint32_t sh_mem_config,
uint32_t sh_mem_ape1_base,
uint32_t sh_mem_ape1_limit,
uint32_t sh_mem_bases)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

lock_srbm(adev, 0, 0, 0, vmid);

WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
Expand All @@ -97,11 +95,9 @@ static void program_sh_mem_settings_v10_3(struct kgd_dev *kgd, uint32_t vmid,
}

/* ATC is defeatured on Sienna_Cichlid */
static int set_pasid_vmid_mapping_v10_3(struct kgd_dev *kgd, unsigned int pasid,
static int set_pasid_vmid_mapping_v10_3(struct amdgpu_device *adev, unsigned int pasid,
unsigned int vmid)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

uint32_t value = pasid << IH_VMID_0_LUT__PASID__SHIFT;

/* Mapping vmid to pasid also for IH block */
Expand All @@ -112,9 +108,8 @@ static int set_pasid_vmid_mapping_v10_3(struct kgd_dev *kgd, unsigned int pasid,
return 0;
}

static int init_interrupts_v10_3(struct kgd_dev *kgd, uint32_t pipe_id)
static int init_interrupts_v10_3(struct amdgpu_device *adev, uint32_t pipe_id)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
uint32_t mec;
uint32_t pipe;

Expand Down Expand Up @@ -593,12 +588,12 @@ static int hqd_sdma_destroy_v10_3(struct amdgpu_device *adev, void *mqd,
}


static int address_watch_disable_v10_3(struct kgd_dev *kgd)
static int address_watch_disable_v10_3(struct amdgpu_device *adev)
{
return 0;
}

static int address_watch_execute_v10_3(struct kgd_dev *kgd,
static int address_watch_execute_v10_3(struct amdgpu_device *adev,
unsigned int watch_point_id,
uint32_t cntl_val,
uint32_t addr_hi,
Expand All @@ -607,11 +602,10 @@ static int address_watch_execute_v10_3(struct kgd_dev *kgd,
return 0;
}

static int wave_control_execute_v10_3(struct kgd_dev *kgd,
static int wave_control_execute_v10_3(struct amdgpu_device *adev,
uint32_t gfx_index_val,
uint32_t sq_cmd)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
uint32_t data = 0;

mutex_lock(&adev->grbm_idx_mutex);
Expand All @@ -632,27 +626,23 @@ static int wave_control_execute_v10_3(struct kgd_dev *kgd,
return 0;
}

static uint32_t address_watch_get_offset_v10_3(struct kgd_dev *kgd,
static uint32_t address_watch_get_offset_v10_3(struct amdgpu_device *adev,
unsigned int watch_point_id,
unsigned int reg_offset)
{
return 0;
}

static void set_vm_context_page_table_base_v10_3(struct kgd_dev *kgd, uint32_t vmid,
uint64_t page_table_base)
static void set_vm_context_page_table_base_v10_3(struct amdgpu_device *adev,
uint32_t vmid, uint64_t page_table_base)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

/* SDMA is on gfxhub as well for Navi1* series */
adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);
}

static void program_trap_handler_settings_v10_3(struct kgd_dev *kgd,
static void program_trap_handler_settings_v10_3(struct amdgpu_device *adev,
uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

lock_srbm(adev, 0, 0, 0, vmid);

/*
Expand All @@ -676,11 +666,10 @@ static void program_trap_handler_settings_v10_3(struct kgd_dev *kgd,
}

#if 0
uint32_t enable_debug_trap_v10_3(struct kgd_dev *kgd,
uint32_t enable_debug_trap_v10_3(struct amdgpu_device *adev,
uint32_t trap_debug_wave_launch_mode,
uint32_t vmid)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
uint32_t data = 0;
uint32_t orig_wave_cntl_value;
uint32_t orig_stall_vmid;
Expand All @@ -707,10 +696,8 @@ uint32_t enable_debug_trap_v10_3(struct kgd_dev *kgd,
return 0;
}

uint32_t disable_debug_trap_v10_3(struct kgd_dev *kgd)
uint32_t disable_debug_trap_v10_3(struct amdgpu_device *adev)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

mutex_lock(&adev->grbm_idx_mutex);

WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
Expand All @@ -720,11 +707,10 @@ uint32_t disable_debug_trap_v10_3(struct kgd_dev *kgd)
return 0;
}

uint32_t set_wave_launch_trap_override_v10_3(struct kgd_dev *kgd,
uint32_t set_wave_launch_trap_override_v10_3(struct amdgpu_device *adev,
uint32_t trap_override,
uint32_t trap_mask)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
uint32_t data = 0;

mutex_lock(&adev->grbm_idx_mutex);
Expand All @@ -749,11 +735,10 @@ uint32_t set_wave_launch_trap_override_v10_3(struct kgd_dev *kgd,
return 0;
}

uint32_t set_wave_launch_mode_v10_3(struct kgd_dev *kgd,
uint32_t set_wave_launch_mode_v10_3(struct amdgpu_device *adev,
uint8_t wave_launch_mode,
uint32_t vmid)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
uint32_t data = 0;
bool is_stall_mode;
bool is_mode_set;
Expand Down Expand Up @@ -792,16 +777,14 @@ uint32_t set_wave_launch_mode_v10_3(struct kgd_dev *kgd,
* sem_rearm_wait_time -- Wait Count for Semaphore re-arm.
* deq_retry_wait_time -- Wait Count for Global Wave Syncs.
*/
void get_iq_wait_times_v10_3(struct kgd_dev *kgd,
void get_iq_wait_times_v10_3(struct amdgpu_device *adev,
uint32_t *wait_times)

{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

*wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));
}

void build_grace_period_packet_info_v10_3(struct kgd_dev *kgd,
void build_grace_period_packet_info_v10_3(struct amdgpu_device *adev,
uint32_t wait_times,
uint32_t grace_period,
uint32_t *reg_offset,
Expand Down
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