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drm/i915/gt: Temporarily disable CPU caching into DMA for MTL
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FIXME: It is suspected that some Address Translation Service (ATS)
issue on IOMMU is causing CAT errors to occur on some MTL workloads.
Applying a write barrier to the ppgtt set entry functions appeared
to have no effect, so we must temporarily use I915_MAP_WC in the
map_pt_dma class of functions on MTL until a proper ATS solution is
found.

Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
CC: Chris Wilson <chris.p.wilson@linux.intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Acked-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231102175831.872763-1-jonathan.cavitt@intel.com
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Jonathan Cavitt authored and Andi Shyti committed Nov 6, 2023
1 parent 27b0863 commit 34df0a0
Showing 1 changed file with 20 additions and 0 deletions.
20 changes: 20 additions & 0 deletions drivers/gpu/drm/i915/gt/intel_gtt.c
Original file line number Diff line number Diff line change
Expand Up @@ -95,6 +95,16 @@ int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
void *vaddr;

type = intel_gt_coherent_map_type(vm->gt, obj, true);
/*
* FIXME: It is suspected that some Address Translation Service (ATS)
* issue on IOMMU is causing CAT errors to occur on some MTL workloads.
* Applying a write barrier to the ppgtt set entry functions appeared
* to have no effect, so we must temporarily use I915_MAP_WC here on
* MTL until a proper ATS solution is found.
*/
if (IS_METEORLAKE(vm->i915))
type = I915_MAP_WC;

vaddr = i915_gem_object_pin_map_unlocked(obj, type);
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
Expand All @@ -109,6 +119,16 @@ int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object
void *vaddr;

type = intel_gt_coherent_map_type(vm->gt, obj, true);
/*
* FIXME: It is suspected that some Address Translation Service (ATS)
* issue on IOMMU is causing CAT errors to occur on some MTL workloads.
* Applying a write barrier to the ppgtt set entry functions appeared
* to have no effect, so we must temporarily use I915_MAP_WC here on
* MTL until a proper ATS solution is found.
*/
if (IS_METEORLAKE(vm->i915))
type = I915_MAP_WC;

vaddr = i915_gem_object_pin_map(obj, type);
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
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