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clk: mediatek: Add MT8195 mfgcfg clock support
Add MT8195 mfg clock controller which provides clock gate control for GPU. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-15-chun-jie.chen@mediatek.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Chun-Jie Chen
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Stephen Boyd
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Sep 14, 2021
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// SPDX-License-Identifier: GPL-2.0-only | ||
// | ||
// Copyright (c) 2021 MediaTek Inc. | ||
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> | ||
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#include "clk-gate.h" | ||
#include "clk-mtk.h" | ||
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#include <dt-bindings/clock/mt8195-clk.h> | ||
#include <linux/clk-provider.h> | ||
#include <linux/platform_device.h> | ||
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static const struct mtk_gate_regs mfg_cg_regs = { | ||
.set_ofs = 0x4, | ||
.clr_ofs = 0x8, | ||
.sta_ofs = 0x0, | ||
}; | ||
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#define GATE_MFG(_id, _name, _parent, _shift) \ | ||
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr) | ||
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static const struct mtk_gate mfg_clks[] = { | ||
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "top_mfg_core_tmp", 0), | ||
}; | ||
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static const struct mtk_clk_desc mfg_desc = { | ||
.clks = mfg_clks, | ||
.num_clks = ARRAY_SIZE(mfg_clks), | ||
}; | ||
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static const struct of_device_id of_match_clk_mt8195_mfg[] = { | ||
{ | ||
.compatible = "mediatek,mt8195-mfgcfg", | ||
.data = &mfg_desc, | ||
}, { | ||
/* sentinel */ | ||
} | ||
}; | ||
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static struct platform_driver clk_mt8195_mfg_drv = { | ||
.probe = mtk_clk_simple_probe, | ||
.driver = { | ||
.name = "clk-mt8195-mfg", | ||
.of_match_table = of_match_clk_mt8195_mfg, | ||
}, | ||
}; | ||
builtin_platform_driver(clk_mt8195_mfg_drv); |