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net: stmmac: dwmac-meson8b: use FIELD_PREP instead of open-coding it
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Use FIELD_PREP() to shift a value to the correct offset based on a
bitmask instead of open-coding the logic.
No functional changes.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Martin Blumenstingl authored and David S. Miller committed May 13, 2020
1 parent ee0b8e6 commit 3649abe
Showing 1 changed file with 3 additions and 2 deletions.
5 changes: 3 additions & 2 deletions drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@
* Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
*/

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
Expand Down Expand Up @@ -32,7 +33,6 @@
#define PRG_ETH0_CLK_M250_SEL_SHIFT 4
#define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)

#define PRG_ETH0_TXDLY_SHIFT 5
#define PRG_ETH0_TXDLY_MASK GENMASK(6, 5)

/* divider for the result of m250_sel */
Expand Down Expand Up @@ -262,7 +262,8 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
PRG_ETH0_INVERTED_RMII_CLK, 0);

meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
FIELD_PREP(PRG_ETH0_TXDLY_MASK,
tx_dly_val));

/* Configure the 125MHz RGMII TX clock, the IP block changes
* the output automatically (= without us having to configure
Expand Down

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