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drm/i915: add panel reset workaround
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Ironlake requires that we clear the reset panel bit during power
sequences and restore it afterwards.  Uncondtionally add code to do that
since it should be harmless on SNB+.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Jesse Barnes committed Aug 18, 2010
1 parent ce17178 commit 37c6c9b
Showing 1 changed file with 16 additions and 1 deletion.
17 changes: 16 additions & 1 deletion drivers/gpu/drm/i915/intel_dp.c
Original file line number Diff line number Diff line change
Expand Up @@ -765,6 +765,12 @@ static void ironlake_edp_panel_on (struct drm_device *dev)
return;

pp = I915_READ(PCH_PP_CONTROL);

/* ILK workaround: disable reset around power sequence */
pp &= ~PANEL_POWER_RESET;
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);

pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
I915_WRITE(PCH_PP_CONTROL, pp);

Expand All @@ -773,7 +779,9 @@ static void ironlake_edp_panel_on (struct drm_device *dev)
I915_READ(PCH_PP_STATUS));

pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
pp |= PANEL_POWER_RESET; /* restore panel reset bit */
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
}

static void ironlake_edp_panel_off (struct drm_device *dev)
Expand All @@ -782,6 +790,12 @@ static void ironlake_edp_panel_off (struct drm_device *dev)
u32 pp;

pp = I915_READ(PCH_PP_CONTROL);

/* ILK workaround: disable reset around power sequence */
pp &= ~PANEL_POWER_RESET;
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);

pp &= ~POWER_TARGET_ON;
I915_WRITE(PCH_PP_CONTROL, pp);

Expand All @@ -790,8 +804,9 @@ static void ironlake_edp_panel_off (struct drm_device *dev)
I915_READ(PCH_PP_STATUS));

/* Make sure VDD is enabled so DP AUX will work */
pp |= EDP_FORCE_VDD;
pp |= EDP_FORCE_VDD | PANEL_POWER_RESET; /* restore panel reset bit */
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
}

static void ironlake_edp_backlight_on (struct drm_device *dev)
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