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mmc: sdhci-of-arasan: Rearrange the platform data structs for modularity
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Existing driver code has the platform specific structures scattered
throughout the driver code. Rearrange the platform specific data
structures for more modularity and readability. This will help in adding
new static functions with more ease.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Link: https://lore.kernel.org/r/1586195015-128992-5-git-send-email-manish.narani@xilinx.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Manish Narani authored and Ulf Hansson committed May 28, 2020
1 parent 19ee441 commit 37d3ee7
Showing 1 changed file with 81 additions and 77 deletions.
158 changes: 81 additions & 77 deletions drivers/mmc/host/sdhci-of-arasan.c
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Original file line number Diff line number Diff line change
Expand Up @@ -346,29 +346,6 @@ static const struct sdhci_ops sdhci_arasan_ops = {
.set_power = sdhci_set_power_and_bus_voltage,
};

static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
.ops = &sdhci_arasan_ops,
.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
SDHCI_QUIRK2_STOP_WITH_TC,
};

static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
.pdata = &sdhci_arasan_pdata,
};

static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
.ops = &sdhci_arasan_ops,
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
SDHCI_QUIRK2_STOP_WITH_TC,
};

static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
.pdata = &sdhci_arasan_zynqmp_pdata,
};

static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
{
int cmd_error = 0;
Expand Down Expand Up @@ -425,21 +402,6 @@ static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
};

static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
.soc_ctl_map = &rk3399_soc_ctl_map,
.pdata = &sdhci_arasan_cqe_pdata,
};

static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
.soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
.pdata = &sdhci_arasan_cqe_pdata,
};

static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
.soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
.pdata = &sdhci_arasan_cqe_pdata,
};

#ifdef CONFIG_PM_SLEEP
/**
* sdhci_arasan_suspend - Suspend method for the driver
Expand Down Expand Up @@ -535,45 +497,6 @@ static int sdhci_arasan_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
sdhci_arasan_resume);

static const struct of_device_id sdhci_arasan_of_match[] = {
/* SoC-specific compatible strings w/ soc_ctl_map */
{
.compatible = "rockchip,rk3399-sdhci-5.1",
.data = &sdhci_arasan_rk3399_data,
},
{
.compatible = "intel,lgm-sdhci-5.1-emmc",
.data = &intel_lgm_emmc_data,
},
{
.compatible = "intel,lgm-sdhci-5.1-sdxc",
.data = &intel_lgm_sdxc_data,
},
/* Generic compatible below here */
{
.compatible = "arasan,sdhci-8.9a",
.data = &sdhci_arasan_generic_data,
},
{
.compatible = "arasan,sdhci-5.1",
.data = &sdhci_arasan_generic_data,
},
{
.compatible = "arasan,sdhci-4.9a",
.data = &sdhci_arasan_generic_data,
},
{
.compatible = "xlnx,zynqmp-8.9a",
.data = &sdhci_arasan_zynqmp_data,
},
{
.compatible = "xlnx,versal-8.9a",
.data = &sdhci_arasan_zynqmp_data,
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);

/**
* sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
*
Expand Down Expand Up @@ -1149,6 +1072,87 @@ static void arasan_dt_parse_clk_phases(struct device *dev,
"clk-phase-mmc-hs400");
}

static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
.ops = &sdhci_arasan_ops,
.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
SDHCI_QUIRK2_STOP_WITH_TC,
};

static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
.pdata = &sdhci_arasan_pdata,
};

static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
.soc_ctl_map = &rk3399_soc_ctl_map,
.pdata = &sdhci_arasan_cqe_pdata,
};

static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
.soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
.pdata = &sdhci_arasan_cqe_pdata,
};

static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
.soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
.pdata = &sdhci_arasan_cqe_pdata,
};

static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
.ops = &sdhci_arasan_ops,
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
SDHCI_QUIRK2_STOP_WITH_TC,
};

static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
.pdata = &sdhci_arasan_zynqmp_pdata,
};

static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
.pdata = &sdhci_arasan_zynqmp_pdata,
};

static const struct of_device_id sdhci_arasan_of_match[] = {
/* SoC-specific compatible strings w/ soc_ctl_map */
{
.compatible = "rockchip,rk3399-sdhci-5.1",
.data = &sdhci_arasan_rk3399_data,
},
{
.compatible = "intel,lgm-sdhci-5.1-emmc",
.data = &intel_lgm_emmc_data,
},
{
.compatible = "intel,lgm-sdhci-5.1-sdxc",
.data = &intel_lgm_sdxc_data,
},
/* Generic compatible below here */
{
.compatible = "arasan,sdhci-8.9a",
.data = &sdhci_arasan_generic_data,
},
{
.compatible = "arasan,sdhci-5.1",
.data = &sdhci_arasan_generic_data,
},
{
.compatible = "arasan,sdhci-4.9a",
.data = &sdhci_arasan_generic_data,
},
{
.compatible = "xlnx,zynqmp-8.9a",
.data = &sdhci_arasan_zynqmp_data,
},
{
.compatible = "xlnx,versal-8.9a",
.data = &sdhci_arasan_versal_data,
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);

/**
* sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
*
Expand Down

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