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drm/i915: Introduce separate status variable for RC6 and LLC ring fre…
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…quency setup

Defined new struct intel_rc6 to hold RC6 specific state and
intel_ring_pstate to hold ring specific state.

v2: s/intel_ring_pstate/intel_llc_pstate. Removed checks from
autoenable_* functions. (Chris)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-13-git-send-email-sagar.a.kamble@intel.com
Acked-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010213010.7415-12-chris@chris-wilson.co.uk
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Sagar Arun Kamble authored and Chris Wilson committed Oct 11, 2017
1 parent fc77426 commit 37d933f
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Showing 3 changed files with 43 additions and 23 deletions.
2 changes: 1 addition & 1 deletion drivers/gpu/drm/i915/i915_drv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2502,7 +2502,7 @@ static int intel_runtime_suspend(struct device *kdev)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret;

if (WARN_ON_ONCE(!(dev_priv->gt_pm.rps.enabled && intel_rc6_enabled())))
if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && intel_rc6_enabled())))
return -ENODEV;

if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
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10 changes: 10 additions & 0 deletions drivers/gpu/drm/i915/i915_drv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1365,8 +1365,18 @@ struct intel_rps {
struct intel_rps_ei ei;
};

struct intel_rc6 {
bool enabled;
};

struct intel_llc_pstate {
bool enabled;
};

struct intel_gen6_power_mgmt {
struct intel_rps rps;
struct intel_rc6 rc6;
struct intel_llc_pstate llc_pstate;
struct delayed_work autoenable_work;
};

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54 changes: 32 additions & 22 deletions drivers/gpu/drm/i915/intel_pm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -7964,7 +7964,8 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)

void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
{
dev_priv->gt_pm.rps.enabled = true; /* force disabling */
dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
intel_disable_gt_powersave(dev_priv);

gen6_reset_rps_interrupts(dev_priv);
Expand All @@ -7974,13 +7975,21 @@ static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
{
lockdep_assert_held(&i915->pcu_lock);

if (!i915->gt_pm.llc_pstate.enabled)
return;

/* Currently there is no HW configuration to be done to disable. */

i915->gt_pm.llc_pstate.enabled = false;
}

static void intel_disable_rc6(struct drm_i915_private *dev_priv)
{
lockdep_assert_held(&dev_priv->pcu_lock);

if (!dev_priv->gt_pm.rc6.enabled)
return;

if (INTEL_GEN(dev_priv) >= 9)
gen9_disable_rc6(dev_priv);
else if (IS_CHERRYVIEW(dev_priv))
Expand All @@ -7989,12 +7998,17 @@ static void intel_disable_rc6(struct drm_i915_private *dev_priv)
valleyview_disable_rc6(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
gen6_disable_rc6(dev_priv);

dev_priv->gt_pm.rc6.enabled = false;
}

static void intel_disable_rps(struct drm_i915_private *dev_priv)
{
lockdep_assert_held(&dev_priv->pcu_lock);

if (!dev_priv->gt_pm.rps.enabled)
return;

if (INTEL_GEN(dev_priv) >= 9)
gen9_disable_rps(dev_priv);
else if (IS_CHERRYVIEW(dev_priv))
Expand All @@ -8005,37 +8019,41 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv)
gen6_disable_rps(dev_priv);
else if (IS_IRONLAKE_M(dev_priv))
ironlake_disable_drps(dev_priv);

dev_priv->gt_pm.rps.enabled = false;
}

void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;

if (!READ_ONCE(rps->enabled))
return;

mutex_lock(&dev_priv->pcu_lock);

intel_disable_rc6(dev_priv);
intel_disable_rps(dev_priv);
if (HAS_LLC(dev_priv))
intel_disable_llc_pstate(dev_priv);

rps->enabled = false;
mutex_unlock(&dev_priv->pcu_lock);
}

static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
{
lockdep_assert_held(&i915->pcu_lock);

if (i915->gt_pm.llc_pstate.enabled)
return;

gen6_update_ring_freq(i915);

i915->gt_pm.llc_pstate.enabled = true;
}

static void intel_enable_rc6(struct drm_i915_private *dev_priv)
{
lockdep_assert_held(&dev_priv->pcu_lock);

if (dev_priv->gt_pm.rc6.enabled)
return;

if (IS_CHERRYVIEW(dev_priv))
cherryview_enable_rc6(dev_priv);
else if (IS_VALLEYVIEW(dev_priv))
Expand All @@ -8046,6 +8064,8 @@ static void intel_enable_rc6(struct drm_i915_private *dev_priv)
gen8_enable_rc6(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
gen6_enable_rc6(dev_priv);

dev_priv->gt_pm.rc6.enabled = true;
}

static void intel_enable_rps(struct drm_i915_private *dev_priv)
Expand All @@ -8054,6 +8074,9 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)

lockdep_assert_held(&dev_priv->pcu_lock);

if (rps->enabled)
return;

if (IS_CHERRYVIEW(dev_priv)) {
cherryview_enable_rps(dev_priv);
} else if (IS_VALLEYVIEW(dev_priv)) {
Expand All @@ -8074,18 +8097,12 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)

WARN_ON(rps->efficient_freq < rps->min_freq);
WARN_ON(rps->efficient_freq > rps->max_freq);

rps->enabled = true;
}

void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;

/* We shouldn't be disabling as we submit, so this should be less
* racy than it appears!
*/
if (READ_ONCE(rps->enabled))
return;

/* Powersaving is controlled by the host when inside a VM */
if (intel_vgpu_active(dev_priv))
return;
Expand All @@ -8097,7 +8114,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
if (HAS_LLC(dev_priv))
intel_enable_llc_pstate(dev_priv);

rps->enabled = true;
mutex_unlock(&dev_priv->pcu_lock);
}

Expand All @@ -8110,9 +8126,6 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
struct intel_engine_cs *rcs;
struct drm_i915_gem_request *req;

if (READ_ONCE(dev_priv->gt_pm.rps.enabled))
goto out;

rcs = dev_priv->engine[RCS];
if (rcs->last_retired_context)
goto out;
Expand Down Expand Up @@ -8140,9 +8153,6 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)

void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
{
if (READ_ONCE(dev_priv->gt_pm.rps.enabled))
return;

if (IS_IRONLAKE_M(dev_priv)) {
ironlake_enable_drps(dev_priv);
intel_init_emon(dev_priv);
Expand Down

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