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* pm-cpuidle: cpuidle: Add 'above' and 'below' idle state metrics cpuidle: big.LITTLE: fix refcount leak cpuidle: Add cpuidle.governor= command line parameter cpuidle: poll_state: Disregard disable idle states Documentation: admin-guide: PM: Add cpuidle document * pm-cpufreq: cpufreq: qcom-hw: Add support for QCOM cpufreq HW driver dt-bindings: cpufreq: Introduce QCOM cpufreq firmware bindings cpufreq: nforce2: Remove meaningless return cpufreq: ia64: Remove unused header files cpufreq: imx6q: save one condition block for normal case of nvmem read cpufreq: imx6q: remove unused code cpufreq: pmac64: add of_node_put() cpufreq: powernv: add of_node_put() Documentation: intel_pstate: Clarify coordination of P-State limits cpufreq: intel_pstate: Force HWP min perf before offline cpufreq: s3c24xx: Change to use DEFINE_SHOW_ATTRIBUTE macro * pm-cpufreq-sched: sched/cpufreq: Add the SPDX tags
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@@ -5,5 +5,6 @@ Working-State Power Management | |
.. toctree:: | ||
:maxdepth: 2 | ||
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cpuidle | ||
cpufreq | ||
intel_pstate |
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Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
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Qualcomm Technologies, Inc. CPUFREQ Bindings | ||
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CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) | ||
SoCs to manage frequency in hardware. It is capable of controlling frequency | ||
for multiple clusters. | ||
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Properties: | ||
- compatible | ||
Usage: required | ||
Value type: <string> | ||
Definition: must be "qcom,cpufreq-hw". | ||
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- clocks | ||
Usage: required | ||
Value type: <phandle> From common clock binding. | ||
Definition: clock handle for XO clock and GPLL0 clock. | ||
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- clock-names | ||
Usage: required | ||
Value type: <string> From common clock binding. | ||
Definition: must be "xo", "alternate". | ||
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- reg | ||
Usage: required | ||
Value type: <prop-encoded-array> | ||
Definition: Addresses and sizes for the memory of the HW bases in | ||
each frequency domain. | ||
- reg-names | ||
Usage: Optional | ||
Value type: <string> | ||
Definition: Frequency domain name i.e. | ||
"freq-domain0", "freq-domain1". | ||
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- #freq-domain-cells: | ||
Usage: required. | ||
Definition: Number of cells in a freqency domain specifier. | ||
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* Property qcom,freq-domain | ||
Devices supporting freq-domain must set their "qcom,freq-domain" property with | ||
phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node. | ||
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Example: | ||
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Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch | ||
DCVS state together. | ||
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/ { | ||
cpus { | ||
#address-cells = <2>; | ||
#size-cells = <0>; | ||
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CPU0: cpu@0 { | ||
device_type = "cpu"; | ||
compatible = "qcom,kryo385"; | ||
reg = <0x0 0x0>; | ||
enable-method = "psci"; | ||
next-level-cache = <&L2_0>; | ||
qcom,freq-domain = <&cpufreq_hw 0>; | ||
L2_0: l2-cache { | ||
compatible = "cache"; | ||
next-level-cache = <&L3_0>; | ||
L3_0: l3-cache { | ||
compatible = "cache"; | ||
}; | ||
}; | ||
}; | ||
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CPU1: cpu@100 { | ||
device_type = "cpu"; | ||
compatible = "qcom,kryo385"; | ||
reg = <0x0 0x100>; | ||
enable-method = "psci"; | ||
next-level-cache = <&L2_100>; | ||
qcom,freq-domain = <&cpufreq_hw 0>; | ||
L2_100: l2-cache { | ||
compatible = "cache"; | ||
next-level-cache = <&L3_0>; | ||
}; | ||
}; | ||
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CPU2: cpu@200 { | ||
device_type = "cpu"; | ||
compatible = "qcom,kryo385"; | ||
reg = <0x0 0x200>; | ||
enable-method = "psci"; | ||
next-level-cache = <&L2_200>; | ||
qcom,freq-domain = <&cpufreq_hw 0>; | ||
L2_200: l2-cache { | ||
compatible = "cache"; | ||
next-level-cache = <&L3_0>; | ||
}; | ||
}; | ||
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CPU3: cpu@300 { | ||
device_type = "cpu"; | ||
compatible = "qcom,kryo385"; | ||
reg = <0x0 0x300>; | ||
enable-method = "psci"; | ||
next-level-cache = <&L2_300>; | ||
qcom,freq-domain = <&cpufreq_hw 0>; | ||
L2_300: l2-cache { | ||
compatible = "cache"; | ||
next-level-cache = <&L3_0>; | ||
}; | ||
}; | ||
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CPU4: cpu@400 { | ||
device_type = "cpu"; | ||
compatible = "qcom,kryo385"; | ||
reg = <0x0 0x400>; | ||
enable-method = "psci"; | ||
next-level-cache = <&L2_400>; | ||
qcom,freq-domain = <&cpufreq_hw 1>; | ||
L2_400: l2-cache { | ||
compatible = "cache"; | ||
next-level-cache = <&L3_0>; | ||
}; | ||
}; | ||
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CPU5: cpu@500 { | ||
device_type = "cpu"; | ||
compatible = "qcom,kryo385"; | ||
reg = <0x0 0x500>; | ||
enable-method = "psci"; | ||
next-level-cache = <&L2_500>; | ||
qcom,freq-domain = <&cpufreq_hw 1>; | ||
L2_500: l2-cache { | ||
compatible = "cache"; | ||
next-level-cache = <&L3_0>; | ||
}; | ||
}; | ||
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CPU6: cpu@600 { | ||
device_type = "cpu"; | ||
compatible = "qcom,kryo385"; | ||
reg = <0x0 0x600>; | ||
enable-method = "psci"; | ||
next-level-cache = <&L2_600>; | ||
qcom,freq-domain = <&cpufreq_hw 1>; | ||
L2_600: l2-cache { | ||
compatible = "cache"; | ||
next-level-cache = <&L3_0>; | ||
}; | ||
}; | ||
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CPU7: cpu@700 { | ||
device_type = "cpu"; | ||
compatible = "qcom,kryo385"; | ||
reg = <0x0 0x700>; | ||
enable-method = "psci"; | ||
next-level-cache = <&L2_700>; | ||
qcom,freq-domain = <&cpufreq_hw 1>; | ||
L2_700: l2-cache { | ||
compatible = "cache"; | ||
next-level-cache = <&L3_0>; | ||
}; | ||
}; | ||
}; | ||
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soc { | ||
cpufreq_hw: cpufreq@17d43000 { | ||
compatible = "qcom,cpufreq-hw"; | ||
reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>; | ||
reg-names = "freq-domain0", "freq-domain1"; | ||
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; | ||
clock-names = "xo", "alternate"; | ||
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#freq-domain-cells = <1>; | ||
}; | ||
} |
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