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dt-bindings: dwmac: Add bindings for new Ingenic SoCs.
Add the dwmac bindings for the JZ4775 SoC, the X1000 SoC, the X1600 SoC, the X1830 SoC and the X2000 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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周琰杰 (Zhou Yanjie)
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David S. Miller
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Jun 14, 2021
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/net/ingenic,mac.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Bindings for MAC in Ingenic SoCs | ||
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maintainers: | ||
- 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> | ||
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description: | ||
The Ethernet Media Access Controller in Ingenic SoCs. | ||
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properties: | ||
compatible: | ||
enum: | ||
- ingenic,jz4775-mac | ||
- ingenic,x1000-mac | ||
- ingenic,x1600-mac | ||
- ingenic,x1830-mac | ||
- ingenic,x2000-mac | ||
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reg: | ||
maxItems: 1 | ||
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interrupts: | ||
maxItems: 1 | ||
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interrupt-names: | ||
const: macirq | ||
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clocks: | ||
maxItems: 1 | ||
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clock-names: | ||
const: stmmaceth | ||
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mode-reg: | ||
description: An extra syscon register that control ethernet interface and timing delay | ||
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rx-clk-delay-ps: | ||
description: RGMII receive clock delay defined in pico seconds | ||
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tx-clk-delay-ps: | ||
description: RGMII transmit clock delay defined in pico seconds | ||
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required: | ||
- compatible | ||
- reg | ||
- interrupts | ||
- interrupt-names | ||
- clocks | ||
- clock-names | ||
- mode-reg | ||
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additionalProperties: false | ||
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examples: | ||
- | | ||
#include <dt-bindings/clock/x1000-cgu.h> | ||
mac: ethernet@134b0000 { | ||
compatible = "ingenic,x1000-mac", "snps,dwmac"; | ||
reg = <0x134b0000 0x2000>; | ||
interrupt-parent = <&intc>; | ||
interrupts = <55>; | ||
interrupt-names = "macirq"; | ||
clocks = <&cgu X1000_CLK_MAC>; | ||
clock-names = "stmmaceth"; | ||
mode-reg = <&mac_phy_ctrl>; | ||
}; | ||
... |
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