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drm/tegra: dpaux: Fix transfers larger than 4 bytes
The DPAUX read/write FIFO registers aren't sequential in the register space, causing transfers larger than 4 bytes to cause accesses to non- existing FIFO registers. Fixes: 6b6b604 ("drm/tegra: Add eDP support") Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding
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Jun 12, 2015
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