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Blackfin: Split PLL code from mach-specific cdef headers
Split the PLL control code from the Blackfin machine-specific cdef headers so that the irqflags functions can be renamed without incurring a header loop. Signed-off-by: David Howells <dhowells@redhat.com>
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David Howells
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Oct 7, 2010
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,63 @@ | ||
| /* | ||
| * Copyright 2008 Analog Devices Inc. | ||
| * | ||
| * Licensed under the GPL-2 or later | ||
| */ | ||
|
|
||
| #ifndef _MACH_PLL_H | ||
| #define _MACH_PLL_H | ||
|
|
||
| #include <asm/blackfin.h> | ||
| #include <asm/irqflags.h> | ||
|
|
||
| /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| { | ||
| unsigned long flags, iwr0, iwr1; | ||
|
|
||
| if (val == bfin_read_PLL_CTL()) | ||
| return; | ||
|
|
||
| local_irq_save_hw(flags); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| iwr0 = bfin_read32(SIC_IWR0); | ||
| iwr1 = bfin_read32(SIC_IWR1); | ||
| /* Only allow PPL Wakeup) */ | ||
| bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| bfin_write32(SIC_IWR1, 0); | ||
|
|
||
| bfin_write16(PLL_CTL, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
|
||
| bfin_write32(SIC_IWR0, iwr0); | ||
| bfin_write32(SIC_IWR1, iwr1); | ||
| local_irq_restore_hw(flags); | ||
| } | ||
|
|
||
| /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| { | ||
| unsigned long flags, iwr0, iwr1; | ||
|
|
||
| if (val == bfin_read_VR_CTL()) | ||
| return; | ||
|
|
||
| local_irq_save_hw(flags); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| iwr0 = bfin_read32(SIC_IWR0); | ||
| iwr1 = bfin_read32(SIC_IWR1); | ||
| /* Only allow PPL Wakeup) */ | ||
| bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| bfin_write32(SIC_IWR1, 0); | ||
|
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| bfin_write16(VR_CTL, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
|
||
| bfin_write32(SIC_IWR0, iwr0); | ||
| bfin_write32(SIC_IWR1, iwr1); | ||
| local_irq_restore_hw(flags); | ||
| } | ||
|
|
||
| #endif /* _MACH_PLL_H */ |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,63 @@ | ||
| /* | ||
| * Copyright 2007-2008 Analog Devices Inc. | ||
| * | ||
| * Licensed under the GPL-2 or later | ||
| */ | ||
|
|
||
| #ifndef _MACH_PLL_H | ||
| #define _MACH_PLL_H | ||
|
|
||
| #include <asm/blackfin.h> | ||
| #include <asm/irqflags.h> | ||
|
|
||
| /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| { | ||
| unsigned long flags, iwr0, iwr1; | ||
|
|
||
| if (val == bfin_read_PLL_CTL()) | ||
| return; | ||
|
|
||
| local_irq_save_hw(flags); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| iwr0 = bfin_read32(SIC_IWR0); | ||
| iwr1 = bfin_read32(SIC_IWR1); | ||
| /* Only allow PPL Wakeup) */ | ||
| bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| bfin_write32(SIC_IWR1, 0); | ||
|
|
||
| bfin_write16(PLL_CTL, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
|
||
| bfin_write32(SIC_IWR0, iwr0); | ||
| bfin_write32(SIC_IWR1, iwr1); | ||
| local_irq_restore_hw(flags); | ||
| } | ||
|
|
||
| /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| { | ||
| unsigned long flags, iwr0, iwr1; | ||
|
|
||
| if (val == bfin_read_VR_CTL()) | ||
| return; | ||
|
|
||
| local_irq_save_hw(flags); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| iwr0 = bfin_read32(SIC_IWR0); | ||
| iwr1 = bfin_read32(SIC_IWR1); | ||
| /* Only allow PPL Wakeup) */ | ||
| bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| bfin_write32(SIC_IWR1, 0); | ||
|
|
||
| bfin_write16(VR_CTL, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
|
||
| bfin_write32(SIC_IWR0, iwr0); | ||
| bfin_write32(SIC_IWR1, iwr1); | ||
| local_irq_restore_hw(flags); | ||
| } | ||
|
|
||
| #endif /* _MACH_PLL_H */ |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,57 @@ | ||
| /* | ||
| * Copyright 2005-2008 Analog Devices Inc. | ||
| * | ||
| * Licensed under the GPL-2 or later | ||
| */ | ||
|
|
||
| #ifndef _MACH_PLL_H | ||
| #define _MACH_PLL_H | ||
|
|
||
| #include <asm/blackfin.h> | ||
| #include <asm/irqflags.h> | ||
|
|
||
| /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| { | ||
| unsigned long flags, iwr; | ||
|
|
||
| if (val == bfin_read_PLL_CTL()) | ||
| return; | ||
|
|
||
| local_irq_save_hw(flags); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| iwr = bfin_read32(SIC_IWR); | ||
| /* Only allow PPL Wakeup) */ | ||
| bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
|
|
||
| bfin_write16(PLL_CTL, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
|
||
| bfin_write32(SIC_IWR, iwr); | ||
| local_irq_restore_hw(flags); | ||
| } | ||
|
|
||
| /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| { | ||
| unsigned long flags, iwr; | ||
|
|
||
| if (val == bfin_read_VR_CTL()) | ||
| return; | ||
|
|
||
| local_irq_save_hw(flags); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| iwr = bfin_read32(SIC_IWR); | ||
| /* Only allow PPL Wakeup) */ | ||
| bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
|
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||
| bfin_write16(VR_CTL, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
|
||
| bfin_write32(SIC_IWR, iwr); | ||
| local_irq_restore_hw(flags); | ||
| } | ||
|
|
||
| #endif /* _MACH_PLL_H */ |
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