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igc: Add interrupt support
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This patch set adds interrupt support for the igc interfaces.

Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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Sasha Neftin authored and Jeff Kirsher committed Oct 17, 2018
1 parent c9a11c2 commit 3df25e4
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127 changes: 127 additions & 0 deletions drivers/net/ethernet/intel/igc/igc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,17 @@
extern char igc_driver_name[];
extern char igc_driver_version[];

/* Interrupt defines */
#define IGC_START_ITR 648 /* ~6000 ints/sec */
#define IGC_FLAG_HAS_MSI BIT(0)
#define IGC_FLAG_QUEUE_PAIRS BIT(4)
#define IGC_FLAG_HAS_MSIX BIT(13)

#define IGC_START_ITR 648 /* ~6000 ints/sec */
#define IGC_4K_ITR 980
#define IGC_20K_ITR 196
#define IGC_70K_ITR 56

/* Transmit and receive queues */
#define IGC_MAX_RX_QUEUES 4
#define IGC_MAX_TX_QUEUES 4
Expand All @@ -42,10 +53,96 @@ enum igc_state_t {
__IGC_PTP_TX_IN_PROGRESS,
};

struct igc_tx_queue_stats {
u64 packets;
u64 bytes;
u64 restart_queue;
};

struct igc_rx_queue_stats {
u64 packets;
u64 bytes;
u64 drops;
u64 csum_err;
u64 alloc_failed;
};

struct igc_rx_packet_stats {
u64 ipv4_packets; /* IPv4 headers processed */
u64 ipv4e_packets; /* IPv4E headers with extensions processed */
u64 ipv6_packets; /* IPv6 headers processed */
u64 ipv6e_packets; /* IPv6E headers with extensions processed */
u64 tcp_packets; /* TCP headers processed */
u64 udp_packets; /* UDP headers processed */
u64 sctp_packets; /* SCTP headers processed */
u64 nfs_packets; /* NFS headers processe */
u64 other_packets;
};

struct igc_ring_container {
struct igc_ring *ring; /* pointer to linked list of rings */
unsigned int total_bytes; /* total bytes processed this int */
unsigned int total_packets; /* total packets processed this int */
u16 work_limit; /* total work allowed per interrupt */
u8 count; /* total number of rings in vector */
u8 itr; /* current ITR setting for ring */
};

struct igc_ring {
struct igc_q_vector *q_vector; /* backlink to q_vector */
struct net_device *netdev; /* back pointer to net_device */
struct device *dev; /* device for dma mapping */
union { /* array of buffer info structs */
struct igc_tx_buffer *tx_buffer_info;
struct igc_rx_buffer *rx_buffer_info;
};
void *desc; /* descriptor ring memory */
unsigned long flags; /* ring specific flags */
void __iomem *tail; /* pointer to ring tail register */
dma_addr_t dma; /* phys address of the ring */
unsigned int size; /* length of desc. ring in bytes */

u16 count; /* number of desc. in the ring */
u8 queue_index; /* logical index of the ring*/
u8 reg_idx; /* physical index of the ring */

/* everything past this point are written often */
u16 next_to_clean;
u16 next_to_use;
u16 next_to_alloc;

union {
/* TX */
struct {
struct igc_tx_queue_stats tx_stats;
};
/* RX */
struct {
struct igc_rx_queue_stats rx_stats;
struct igc_rx_packet_stats pkt_stats;
struct sk_buff *skb;
};
};
} ____cacheline_internodealigned_in_smp;

struct igc_q_vector {
struct igc_adapter *adapter; /* backlink */
void __iomem *itr_register;
u32 eims_value; /* EIMS mask value */

u16 itr_val;
u8 set_itr;

struct igc_ring_container rx, tx;

struct napi_struct napi;

struct rcu_head rcu; /* to avoid race with update stats on free */
char name[IFNAMSIZ + 9];
struct net_device poll_dev;

/* for dynamic allocation of rings associated with this q_vector */
struct igc_ring ring[0] ____cacheline_internodealigned_in_smp;
};

struct igc_mac_addr {
Expand All @@ -65,13 +162,35 @@ struct igc_adapter {
unsigned long state;
unsigned int flags;
unsigned int num_q_vectors;

struct msix_entry *msix_entries;

/* TX */
u16 tx_work_limit;
int num_tx_queues;
struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];

/* RX */
int num_rx_queues;
struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];

struct timer_list watchdog_timer;
struct timer_list dma_err_timer;
struct timer_list phy_info_timer;

u16 link_speed;
u16 link_duplex;

u8 port_num;

u8 __iomem *io_addr;
/* Interrupt Throttle Rate */
u32 rx_itr_setting;
u32 tx_itr_setting;

struct work_struct reset_task;
struct work_struct watchdog_task;
struct work_struct dma_err_task;

int msg_enable;
u32 max_frame_size;
Expand All @@ -81,8 +200,16 @@ struct igc_adapter {

/* structs defined in igc_hw.h */
struct igc_hw hw;
struct igc_hw_stats stats;

struct igc_q_vector *q_vector[MAX_Q_VECTORS];
u32 eims_enable_mask;
u32 eims_other;

u16 tx_ring_count;
u16 rx_ring_count;

u32 rss_queues;

struct igc_mac_addr *mac_table;
};
Expand Down
40 changes: 40 additions & 0 deletions drivers/net/ethernet/intel/igc/igc_defines.h
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Original file line number Diff line number Diff line change
Expand Up @@ -42,4 +42,44 @@
#define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
#define IGC_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */

/* Interrupt Cause Read */
#define IGC_ICR_TXDW BIT(0) /* Transmit desc written back */
#define IGC_ICR_TXQE BIT(1) /* Transmit Queue empty */
#define IGC_ICR_LSC BIT(2) /* Link Status Change */
#define IGC_ICR_RXSEQ BIT(3) /* Rx sequence error */
#define IGC_ICR_RXDMT0 BIT(4) /* Rx desc min. threshold (0) */
#define IGC_ICR_RXO BIT(6) /* Rx overrun */
#define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */
#define IGC_ICR_DRSTA BIT(30) /* Device Reset Asserted */
#define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */

#define IMS_ENABLE_MASK ( \
IGC_IMS_RXT0 | \
IGC_IMS_TXDW | \
IGC_IMS_RXDMT0 | \
IGC_IMS_RXSEQ | \
IGC_IMS_LSC)

/* Interrupt Mask Set */
#define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */
#define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
#define IGC_IMS_LSC IGC_ICR_LSC /* Link Status Change */
#define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */
#define IGC_IMS_DRSTA IGC_ICR_DRSTA /* Device Reset Asserted */
#define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
#define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */

#define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
#define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */

#define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
#define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
#define IGC_IVAR_VALID 0x80
#define IGC_GPIE_NSICR 0x00000001
#define IGC_GPIE_MSIX_MODE 0x00000010
#define IGC_GPIE_EIAME 0x40000000
#define IGC_GPIE_PBA 0x80000000

#define IGC_N0_QUEUE -1

#endif /* _IGC_DEFINES_H_ */
84 changes: 84 additions & 0 deletions drivers/net/ethernet/intel/igc/igc_hw.h
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Original file line number Diff line number Diff line change
Expand Up @@ -85,6 +85,90 @@ struct igc_hw {
u8 revision_id;
};

/* Statistics counters collected by the MAC */
struct igc_hw_stats {
u64 crcerrs;
u64 algnerrc;
u64 symerrs;
u64 rxerrc;
u64 mpc;
u64 scc;
u64 ecol;
u64 mcc;
u64 latecol;
u64 colc;
u64 dc;
u64 tncrs;
u64 sec;
u64 cexterr;
u64 rlec;
u64 xonrxc;
u64 xontxc;
u64 xoffrxc;
u64 xofftxc;
u64 fcruc;
u64 prc64;
u64 prc127;
u64 prc255;
u64 prc511;
u64 prc1023;
u64 prc1522;
u64 gprc;
u64 bprc;
u64 mprc;
u64 gptc;
u64 gorc;
u64 gotc;
u64 rnbc;
u64 ruc;
u64 rfc;
u64 roc;
u64 rjc;
u64 mgprc;
u64 mgpdc;
u64 mgptc;
u64 tor;
u64 tot;
u64 tpr;
u64 tpt;
u64 ptc64;
u64 ptc127;
u64 ptc255;
u64 ptc511;
u64 ptc1023;
u64 ptc1522;
u64 mptc;
u64 bptc;
u64 tsctc;
u64 tsctfc;
u64 iac;
u64 icrxptc;
u64 icrxatc;
u64 ictxptc;
u64 ictxatc;
u64 ictxqec;
u64 ictxqmtc;
u64 icrxdmtc;
u64 icrxoc;
u64 cbtmpc;
u64 htdpmc;
u64 cbrdpc;
u64 cbrmpc;
u64 rpthc;
u64 hgptc;
u64 htcbdpc;
u64 hgorc;
u64 hgotc;
u64 lenerrs;
u64 scvpc;
u64 hrmpc;
u64 doosync;
u64 o2bgptc;
u64 o2bspc;
u64 b2ospc;
u64 b2ogprc;
};

s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
Expand Down
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