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serial: 8250_dw: Introduce IO accessors to extended registers
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There are several extended (in comparison to the traditional 16550)
registers are present in Synopsys DesignWare UART. All of them
are 32-bit ones.

Introduce helpers to simplify access to them and convert existing users.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Andy Shevchenko authored and Greg Kroah-Hartman committed Jul 7, 2018
1 parent 447735f commit 3ff1070
Showing 1 changed file with 17 additions and 8 deletions.
25 changes: 17 additions & 8 deletions drivers/tty/serial/8250/8250_dw.c
Original file line number Diff line number Diff line change
@@ -67,6 +67,21 @@ struct dw8250_data {
unsigned int uart_16550_compatible:1;
};

static inline u32 dw8250_readl_ext(struct uart_port *p, int offset)
{
if (p->iotype == UPIO_MEM32BE)
return ioread32be(p->membase + offset);
return readl(p->membase + offset);
}

static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
{
if (p->iotype == UPIO_MEM32BE)
iowrite32be(reg, p->membase + offset);
else
writel(reg, p->membase + offset);
}

static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
{
struct dw8250_data *d = p->private_data;
@@ -404,20 +419,14 @@ static void dw8250_setup_port(struct uart_port *p)
* If the Component Version Register returns zero, we know that
* ADDITIONAL_FEATURES are not enabled. No need to go any further.
*/
if (p->iotype == UPIO_MEM32BE)
reg = ioread32be(p->membase + DW_UART_UCV);
else
reg = readl(p->membase + DW_UART_UCV);
reg = dw8250_readl_ext(p, DW_UART_UCV);
if (!reg)
return;

dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
(reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);

if (p->iotype == UPIO_MEM32BE)
reg = ioread32be(p->membase + DW_UART_CPR);
else
reg = readl(p->membase + DW_UART_CPR);
reg = dw8250_readl_ext(p, DW_UART_CPR);
if (!reg)
return;

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