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Merge branch 'clk-qcom' into clk-next
* clk-qcom: (87 commits) clk: qcom: Fix SM_GPUCC_8450 dependencies clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags clk: qcom: gcc-ipq5018: change some variable static clk: qcom: gcc-ipq4019: add missing networking resets dt-bindings: clock: qcom: ipq4019: add missing networking resets clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC clk: qcom: gcc-qdu1000: Update the RCGs ops clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops clk: qcom: gcc-qdu1000: Add support for GDSCs clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock clk: qcom: gcc-qdu1000: Fix clkref clocks handling clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock clk: qcom: ipq5332: drop the mem noc clocks clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks ...
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Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
||
title: Qualcomm Global Clock & Reset Controller on IPQ5018 | ||
|
||
maintainers: | ||
- Sricharan Ramabadhran <quic_srichara@quicinc.com> | ||
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||
description: | | ||
Qualcomm global clock control module provides the clocks, resets and power | ||
domains on IPQ5018 | ||
See also:: | ||
include/dt-bindings/clock/qcom,ipq5018-gcc.h | ||
include/dt-bindings/reset/qcom,ipq5018-gcc.h | ||
properties: | ||
compatible: | ||
const: qcom,gcc-ipq5018 | ||
|
||
clocks: | ||
items: | ||
- description: Board XO source | ||
- description: Sleep clock source | ||
- description: PCIE20 PHY0 pipe clock source | ||
- description: PCIE20 PHY1 pipe clock source | ||
- description: USB3 PHY pipe clock source | ||
- description: GEPHY RX clock source | ||
- description: GEPHY TX clock source | ||
- description: UNIPHY RX clock source | ||
- description: UNIPHY TX clk source | ||
|
||
required: | ||
- compatible | ||
- clocks | ||
|
||
allOf: | ||
- $ref: qcom,gcc.yaml# | ||
|
||
unevaluatedProperties: false | ||
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||
examples: | ||
- | | ||
clock-controller@1800000 { | ||
compatible = "qcom,gcc-ipq5018"; | ||
reg = <0x01800000 0x80000>; | ||
clocks = <&xo_board_clk>, | ||
<&sleep_clk>, | ||
<&pcie20_phy0_pipe_clk>, | ||
<&pcie20_phy1_pipe_clk>, | ||
<&usb3_phy0_pipe_clk>, | ||
<&gephy_rx_clk>, | ||
<&gephy_tx_clk>, | ||
<&uniphy_rx_clk>, | ||
<&uniphy_tx_clk>; | ||
#clock-cells = <1>; | ||
#reset-cells = <1>; | ||
#power-domain-cells = <1>; | ||
}; | ||
... |
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