Skip to content

Commit

Permalink
clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple o…
Browse files Browse the repository at this point in the history
…utputs

Some of the SAMA7G5 PLLs support multiple outputs (e.g. AUDIO PLL).
For these, split the PLL clock in two: fractional clock and
divider clock. In case PLLs supports multiple outputs (since these
outputs are dividers (with different settings) sharing the same
fractional part), it will register one fractional clock and multiple
divider clocks (dividers sharing the fractional clock).

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-17-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  • Loading branch information
Claudiu Beznea authored and Stephen Boyd committed Jul 24, 2020
1 parent 0416824 commit 43b1bb4
Show file tree
Hide file tree
Showing 3 changed files with 433 additions and 186 deletions.
Loading

0 comments on commit 43b1bb4

Please sign in to comment.