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soc: renesas: rcar-sysc: Add support for R-Car E3 power areas
This patch adds Cortex-A53 CPU{0,1}, Cortex-A53 SCU, Cortex-R7, A3VC, A2VC1 and 3DG-{A,B} power domain areas for the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [shimoda: fix 3DG-{A,B} and add SPDX-License-Identifier] Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Takeshi Kihara
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Simon Horman
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May 16, 2018
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// SPDX-License-Identifier: GPL-2.0 | ||
/* | ||
* Renesas R-Car E3 System Controller | ||
* | ||
* Copyright (C) 2018 Renesas Electronics Corp. | ||
*/ | ||
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#include <linux/bug.h> | ||
#include <linux/kernel.h> | ||
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#include <dt-bindings/power/r8a77990-sysc.h> | ||
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#include "rcar-sysc.h" | ||
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static const struct rcar_sysc_area r8a77990_areas[] __initconst = { | ||
{ "always-on", 0, 0, R8A77990_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, | ||
{ "ca53-scu", 0x140, 0, R8A77990_PD_CA53_SCU, R8A77990_PD_ALWAYS_ON, | ||
PD_SCU }, | ||
{ "ca53-cpu0", 0x200, 0, R8A77990_PD_CA53_CPU0, R8A77990_PD_CA53_SCU, | ||
PD_CPU_NOCR }, | ||
{ "ca53-cpu1", 0x200, 1, R8A77990_PD_CA53_CPU1, R8A77990_PD_CA53_SCU, | ||
PD_CPU_NOCR }, | ||
{ "cr7", 0x240, 0, R8A77990_PD_CR7, R8A77990_PD_ALWAYS_ON }, | ||
{ "a3vc", 0x380, 0, R8A77990_PD_A3VC, R8A77990_PD_ALWAYS_ON }, | ||
{ "a2vc1", 0x3c0, 1, R8A77990_PD_A2VC1, R8A77990_PD_A3VC }, | ||
{ "3dg-a", 0x100, 0, R8A77990_PD_3DG_A, R8A77990_PD_ALWAYS_ON }, | ||
{ "3dg-b", 0x100, 1, R8A77990_PD_3DG_B, R8A77990_PD_3DG_A }, | ||
}; | ||
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const struct rcar_sysc_info r8a77990_sysc_info __initconst = { | ||
.areas = r8a77990_areas, | ||
.num_areas = ARRAY_SIZE(r8a77990_areas), | ||
}; |
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