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ARM: dts: omap3: Fix NAND device nodes
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Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.

The GPMC node will provide an interrupt controller for the
NAND IRQs.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Roger Quadros authored and Tony Lindgren committed Feb 26, 2016
1 parent 6607fac commit 44e4716
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Showing 17 changed files with 75 additions and 17 deletions.
3 changes: 2 additions & 1 deletion arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
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Expand Up @@ -93,7 +93,8 @@
};

&gpmc {
ranges = <1 0 0x08000000 0x1000000>; /* CS1: 16MB for LAN9221 */
ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */
1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */

ethernet@gpmc {
pinctrl-names = "default";
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8 changes: 6 additions & 2 deletions arch/arm/boot/dts/logicpd-torpedo-som.dtsi
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Expand Up @@ -35,11 +35,15 @@
};

&gpmc {
ranges = <0 0 0x00000000 0x1000000>; /* CS0: 16MB for NAND */
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */

nand@0,0 {
linux,mtd-name = "micron,mt29f4g16abbda3w";
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
linux,mtd-name = "micron,mt29f4g16abbda3w";
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";
gpmc,sync-clk-ps = <0>;
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5 changes: 4 additions & 1 deletion arch/arm/boot/dts/omap3-beagle.dts
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Expand Up @@ -384,8 +384,11 @@

/* Chip select 0 */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* NAND I/O window, 4 bytes */
interrupts = <20>;
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
ti,nand-ecc-opt = "ham1";
nand-bus-width = <16>;
#address-cells = <1>;
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6 changes: 5 additions & 1 deletion arch/arm/boot/dts/omap3-cm-t3x.dtsi
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Expand Up @@ -261,10 +261,14 @@
};

&gpmc {
ranges = <0 0 0x00000000 0x01000000>;
ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */

nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
nand-bus-width = <8>;
gpmc,device-width = <1>;
ti,nand-ecc-opt = "sw";
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4 changes: 4 additions & 0 deletions arch/arm/boot/dts/omap3-devkit8000-common.dtsi
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Expand Up @@ -204,7 +204,11 @@
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */

nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "sw";
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8 changes: 6 additions & 2 deletions arch/arm/boot/dts/omap3-evm-37xx.dts
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Expand Up @@ -154,12 +154,16 @@
};

&gpmc {
ranges = <0 0 0x00000000 0x1000000>, /* CS0: 16MB for NAND */
ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */
<5 0 0x2c000000 0x01000000>;

nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
linux,mtd-name= "hynix,h8kds0un0mer-4em";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "bch8";
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4 changes: 4 additions & 0 deletions arch/arm/boot/dts/omap3-gta04.dtsi
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Expand Up @@ -492,7 +492,11 @@
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */

nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";

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6 changes: 5 additions & 1 deletion arch/arm/boot/dts/omap3-igep.dtsi
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Expand Up @@ -95,8 +95,12 @@

&gpmc {
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
linux,mtd-name= "micron,mt29c4g96maz";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "bch8";
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4 changes: 2 additions & 2 deletions arch/arm/boot/dts/omap3-igep0020-common.dtsi
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Expand Up @@ -210,8 +210,8 @@
};

&gpmc {
ranges = <0 0 0x00000000 0x20000000>,
<5 0 0x2c000000 0x01000000>;
ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */
<5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */

ethernet@gpmc {
pinctrl-names = "default";
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4 changes: 4 additions & 0 deletions arch/arm/boot/dts/omap3-igep0030-common.dtsi
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Expand Up @@ -58,3 +58,7 @@
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};

&gpmc {
ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */
};
10 changes: 7 additions & 3 deletions arch/arm/boot/dts/omap3-ldp.dts
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Expand Up @@ -97,12 +97,16 @@
};

&gpmc {
ranges = <0 0 0x00000000 0x01000000>,
<1 0 0x08000000 0x01000000>;
ranges = <0 0 0x30000000 0x1000000>, /* CS0 space, 16MB */
<1 0 0x08000000 0x1000000>; /* CS1 space, 16MB */

nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
linux,mtd-name= "micron,nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "bch8";
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6 changes: 5 additions & 1 deletion arch/arm/boot/dts/omap3-lilly-a83x.dtsi
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Expand Up @@ -362,7 +362,11 @@
<7 0 0x15000000 0x01000000>;

nand@0,0 {
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";
/* no elm on omap3 */
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6 changes: 5 additions & 1 deletion arch/arm/boot/dts/omap3-overo-base.dtsi
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Expand Up @@ -226,8 +226,12 @@
ranges = <0 0 0x00000000 0x20000000>;

nand@0,0 {
compatible = "ti,omap2-nand";
linux,mtd-name= "micron,mt29c4g96maz";
reg = <0 0 0>;
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "bch8";
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4 changes: 4 additions & 0 deletions arch/arm/boot/dts/omap3-pandora-common.dtsi
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Expand Up @@ -546,7 +546,11 @@
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */

nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
nand-bus-width = <16>;
ti,nand-ecc-opt = "sw";

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6 changes: 5 additions & 1 deletion arch/arm/boot/dts/omap3-tao3530.dtsi
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Expand Up @@ -275,10 +275,14 @@
};

&gpmc {
ranges = <0 0 0x00000000 0x01000000>;
ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */

nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
nand-bus-width = <16>;
gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
ti,nand-ecc-opt = "sw";
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2 changes: 2 additions & 0 deletions arch/arm/boot/dts/omap3.dtsi
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Expand Up @@ -723,6 +723,8 @@
gpmc,num-waitpins = <4>;
#address-cells = <2>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
};

usb_otg_hs: usb_otg_hs@480ab000 {
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6 changes: 5 additions & 1 deletion arch/arm/boot/dts/omap3430-sdp.dts
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Expand Up @@ -103,10 +103,14 @@
};

nand@1,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
linux,mtd-name= "micron,mt29f1g08abb";
#address-cells = <1>;
#size-cells = <1>;
reg = <1 0 4>; /* CS1, offset 0, IO size 4 */
ti,nand-ecc-opt = "sw";
nand-bus-width = <8>;
gpmc,cs-on-ns = <0>;
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