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drm/amd/display: Fix B0 USB-C DP Alt mode
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[Why]
Starting from B0, along with RDPCSTX, RDPCSPIPE registers are also used.

[How]
Make sure RDPCSPIPE registers are programmed correctly.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Zhan Liu <Zhan.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
(cherry picked from commit bdd1a21)
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Liu, Zhan authored and Alex Deucher committed Oct 5, 2021
1 parent 9e1ff30 commit 45d65c0
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Showing 4 changed files with 70 additions and 2 deletions.
1 change: 1 addition & 0 deletions drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
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Original file line number Diff line number Diff line change
Expand Up @@ -118,6 +118,7 @@ struct dcn10_link_enc_registers {
uint32_t RDPCSTX_PHY_CNTL4;
uint32_t RDPCSTX_PHY_CNTL5;
uint32_t RDPCSTX_PHY_CNTL6;
uint32_t RDPCSPIPE_PHY_CNTL6;
uint32_t RDPCSTX_PHY_CNTL7;
uint32_t RDPCSTX_PHY_CNTL8;
uint32_t RDPCSTX_PHY_CNTL9;
Expand Down
33 changes: 32 additions & 1 deletion drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
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Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@

#include "link_enc_cfg.h"
#include "dc_dmub_srv.h"
#include "dal_asic_id.h"

#define CTX \
enc10->base.ctx
Expand Down Expand Up @@ -215,7 +216,7 @@ static const struct link_encoder_funcs dcn31_link_enc_funcs = {
.fec_is_active = enc2_fec_is_active,
.get_dig_frontend = dcn10_get_dig_frontend,
.get_dig_mode = dcn10_get_dig_mode,
.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
.is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,
.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
};
Expand Down Expand Up @@ -404,3 +405,33 @@ void dcn31_link_encoder_disable_output(
}
}

bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder *enc)
{
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
uint32_t dp_alt_mode_disable;
bool is_usb_c_alt_mode = false;

if (enc->features.flags.bits.DP_IS_USB_C) {
if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
// [Note] no need to check hw_internal_rev once phy mux selection is ready
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
} else {
/*
* B0 phys use a new set of registers to check whether alt mode is disabled.
* if value == 1 alt mode is disabled, otherwise it is enabled.
*/
if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)
|| (enc10->base.transmitter == TRANSMITTER_UNIPHY_B)
|| (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
} else {
// [Note] need to change TRANSMITTER_UNIPHY_C/D to F/G once phy mux selection is ready
REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
}
}

is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
}

return is_usb_c_alt_mode;
}
11 changes: 10 additions & 1 deletion drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
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Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,7 @@
SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \
SRI(RDPCSPIPE_PHY_CNTL6, RDPCSPIPE, id), \
SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \
SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \
SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \
Expand Down Expand Up @@ -115,7 +116,9 @@
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE_ACK, mask_sh),\
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, mask_sh),\
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, mask_sh),\
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, mask_sh),\
Expand Down Expand Up @@ -243,4 +246,10 @@ void dcn31_link_encoder_disable_output(
struct link_encoder *enc,
enum signal_type signal);

/*
* Check whether USB-C DP Alt mode is disabled
*/
bool dcn31_link_encoder_is_in_alt_mode(
struct link_encoder *enc);

#endif /* __DC_LINK_ENCODER__DCN31_H__ */
27 changes: 27 additions & 0 deletions drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h
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Original file line number Diff line number Diff line change
Expand Up @@ -11932,5 +11932,32 @@
#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7
#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8

//RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6
#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10
#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11
#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12
#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L
#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L
#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L

//RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6
#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10
#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11
#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12
#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L
#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L
#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L

//[Note] Hack. RDPCSPIPE only has 2 instances.
#define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6 0x2d73
#define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2
#define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6 0x2e4b
#define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2
#define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6 0x2d73
#define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2
#define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6 0x2e4b
#define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2
#define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6 0x2d73
#define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2

#endif

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