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iwlwifi: mvm: update definitions due to new rate & flags
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As a part of preparing to the new rate & flags version
Update the relevant definitions and use them.

Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://lore.kernel.org/r/iwlwifi.20211017123741.5862bf4f14c4.Ib476b5443faa085539b79d49a0aebd81a213b42f@changeid
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
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Miri Korenblit authored and Luca Coelho committed Oct 22, 2021
1 parent 12d60c1 commit 48c6ebc
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Showing 9 changed files with 147 additions and 147 deletions.
58 changes: 29 additions & 29 deletions drivers/net/wireless/intel/iwlwifi/fw/api/rs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -248,7 +248,7 @@ enum {
};

/*
* rate_n_flags bit fields
* rate_n_flags bit fields version 1
*
* The 32-bit value has different layouts in the low 8 bites depending on the
* format. There are three formats, HT, VHT and legacy (11abg, with subformats
Expand All @@ -266,15 +266,15 @@ enum {

/* Bit 8: (1) HT format, (0) legacy or VHT format */
#define RATE_MCS_HT_POS 8
#define RATE_MCS_HT_MSK (1 << RATE_MCS_HT_POS)
#define RATE_MCS_HT_MSK_V1 BIT(RATE_MCS_HT_POS)

/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
#define RATE_MCS_CCK_POS 9
#define RATE_MCS_CCK_MSK (1 << RATE_MCS_CCK_POS)
#define RATE_MCS_CCK_POS_V1 9
#define RATE_MCS_CCK_MSK_V1 BIT(RATE_MCS_CCK_POS_V1)

/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
#define RATE_MCS_VHT_POS 26
#define RATE_MCS_VHT_MSK (1 << RATE_MCS_VHT_POS)
#define RATE_MCS_VHT_POS_V1 26
#define RATE_MCS_VHT_MSK_V1 BIT(RATE_MCS_VHT_POS_V1)


/*
Expand All @@ -300,15 +300,15 @@ enum {
* streams and 16-23 have three streams. We could also support MCS 32
* which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
*/
#define RATE_HT_MCS_RATE_CODE_MSK 0x7
#define RATE_HT_MCS_NSS_POS 3
#define RATE_HT_MCS_NSS_MSK (3 << RATE_HT_MCS_NSS_POS)
#define RATE_HT_MCS_RATE_CODE_MSK_V1 0x7
#define RATE_HT_MCS_NSS_POS_V1 3
#define RATE_HT_MCS_NSS_MSK_V1 (3 << RATE_HT_MCS_NSS_POS_V1)

/* Bit 10: (1) Use Green Field preamble */
#define RATE_HT_MCS_GF_POS 10
#define RATE_HT_MCS_GF_MSK (1 << RATE_HT_MCS_GF_POS)

#define RATE_HT_MCS_INDEX_MSK 0x3f
#define RATE_HT_MCS_INDEX_MSK_V1 0x3f

/*
* Very High-throughput (VHT) rate format for bits 7:0
Expand Down Expand Up @@ -347,26 +347,26 @@ enum {
* 110) 11 Mbps
* (bit 7 is 0)
*/
#define RATE_LEGACY_RATE_MSK 0xff
#define RATE_LEGACY_RATE_MSK_V1 0xff

/* Bit 10 - OFDM HE */
#define RATE_MCS_HE_POS 10
#define RATE_MCS_HE_MSK BIT(RATE_MCS_HE_POS)
#define RATE_MCS_HE_POS_V1 10
#define RATE_MCS_HE_MSK_V1 BIT(RATE_MCS_HE_POS_V1)

/*
* Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
* 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
*/
#define RATE_MCS_CHAN_WIDTH_POS 11
#define RATE_MCS_CHAN_WIDTH_MSK (3 << RATE_MCS_CHAN_WIDTH_POS)
#define RATE_MCS_CHAN_WIDTH_MSK_V1 (3 << RATE_MCS_CHAN_WIDTH_POS)
#define RATE_MCS_CHAN_WIDTH_20 (0 << RATE_MCS_CHAN_WIDTH_POS)
#define RATE_MCS_CHAN_WIDTH_40 (1 << RATE_MCS_CHAN_WIDTH_POS)
#define RATE_MCS_CHAN_WIDTH_80 (2 << RATE_MCS_CHAN_WIDTH_POS)
#define RATE_MCS_CHAN_WIDTH_160 (3 << RATE_MCS_CHAN_WIDTH_POS)

/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
#define RATE_MCS_SGI_POS 13
#define RATE_MCS_SGI_MSK (1 << RATE_MCS_SGI_POS)
#define RATE_MCS_SGI_POS_V1 13
#define RATE_MCS_SGI_MSK_V1 BIT(RATE_MCS_SGI_POS_V1)

/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
#define RATE_MCS_ANT_POS 14
Expand Down Expand Up @@ -408,27 +408,27 @@ enum {
* 3 (does not occur)
*/
#define RATE_MCS_HE_GI_LTF_POS 20
#define RATE_MCS_HE_GI_LTF_MSK (3 << RATE_MCS_HE_GI_LTF_POS)
#define RATE_MCS_HE_GI_LTF_MSK_V1 (3 << RATE_MCS_HE_GI_LTF_POS)

/* Bit 22-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */
#define RATE_MCS_HE_TYPE_POS 22
#define RATE_MCS_HE_TYPE_SU (0 << RATE_MCS_HE_TYPE_POS)
#define RATE_MCS_HE_TYPE_EXT_SU (1 << RATE_MCS_HE_TYPE_POS)
#define RATE_MCS_HE_TYPE_MU (2 << RATE_MCS_HE_TYPE_POS)
#define RATE_MCS_HE_TYPE_TRIG (3 << RATE_MCS_HE_TYPE_POS)
#define RATE_MCS_HE_TYPE_MSK (3 << RATE_MCS_HE_TYPE_POS)
#define RATE_MCS_HE_TYPE_POS_V1 22
#define RATE_MCS_HE_TYPE_SU_V1 (0 << RATE_MCS_HE_TYPE_POS_V1)
#define RATE_MCS_HE_TYPE_EXT_SU_V1 BIT(RATE_MCS_HE_TYPE_POS_V1)
#define RATE_MCS_HE_TYPE_MU_V1 (2 << RATE_MCS_HE_TYPE_POS_V1)
#define RATE_MCS_HE_TYPE_TRIG_V1 (3 << RATE_MCS_HE_TYPE_POS_V1)
#define RATE_MCS_HE_TYPE_MSK_V1 (3 << RATE_MCS_HE_TYPE_POS_V1)

/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
#define RATE_MCS_DUP_POS 24
#define RATE_MCS_DUP_MSK (3 << RATE_MCS_DUP_POS)
#define RATE_MCS_DUP_POS_V1 24
#define RATE_MCS_DUP_MSK_V1 (3 << RATE_MCS_DUP_POS_V1)

/* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
#define RATE_MCS_LDPC_POS 27
#define RATE_MCS_LDPC_MSK (1 << RATE_MCS_LDPC_POS)
#define RATE_MCS_LDPC_POS_V1 27
#define RATE_MCS_LDPC_MSK_V1 BIT(RATE_MCS_LDPC_POS_V1)

/* Bit 28: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */
#define RATE_MCS_HE_106T_POS 28
#define RATE_MCS_HE_106T_MSK (1 << RATE_MCS_HE_106T_POS)
#define RATE_MCS_HE_106T_POS_V1 28
#define RATE_MCS_HE_106T_MSK_V1 BIT(RATE_MCS_HE_106T_POS_V1)

/* Bit 30-31: (1) RTS, (2) CTS */
#define RATE_MCS_RTS_REQUIRED_POS (30)
Expand Down
2 changes: 1 addition & 1 deletion drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -846,7 +846,7 @@ static void iwl_mvm_mac_ctxt_set_tx(struct iwl_mvm *mvm,

tx->rate_n_flags |= cpu_to_le32(iwl_mvm_mac80211_idx_to_hwrate(rate));
if (rate == IWL_FIRST_CCK_RATE)
tx->rate_n_flags |= cpu_to_le32(RATE_MCS_CCK_MSK);
tx->rate_n_flags |= cpu_to_le32(RATE_MCS_CCK_MSK_V1);

}

Expand Down
34 changes: 17 additions & 17 deletions drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
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Original file line number Diff line number Diff line change
Expand Up @@ -4878,7 +4878,7 @@ static int iwl_mvm_mac_get_survey(struct ieee80211_hw *hw, int idx,

static void iwl_mvm_set_sta_rate(u32 rate_n_flags, struct rate_info *rinfo)
{
switch (rate_n_flags & RATE_MCS_CHAN_WIDTH_MSK) {
switch (rate_n_flags & RATE_MCS_CHAN_WIDTH_MSK_V1) {
case RATE_MCS_CHAN_WIDTH_20:
rinfo->bw = RATE_INFO_BW_20;
break;
Expand All @@ -4893,57 +4893,57 @@ static void iwl_mvm_set_sta_rate(u32 rate_n_flags, struct rate_info *rinfo)
break;
}

if (rate_n_flags & RATE_MCS_HT_MSK) {
if (rate_n_flags & RATE_MCS_HT_MSK_V1) {
rinfo->flags |= RATE_INFO_FLAGS_MCS;
rinfo->mcs = u32_get_bits(rate_n_flags, RATE_HT_MCS_INDEX_MSK);
rinfo->mcs = u32_get_bits(rate_n_flags, RATE_HT_MCS_INDEX_MSK_V1);
rinfo->nss = u32_get_bits(rate_n_flags,
RATE_HT_MCS_NSS_MSK) + 1;
if (rate_n_flags & RATE_MCS_SGI_MSK)
RATE_HT_MCS_NSS_MSK_V1) + 1;
if (rate_n_flags & RATE_MCS_SGI_MSK_V1)
rinfo->flags |= RATE_INFO_FLAGS_SHORT_GI;
} else if (rate_n_flags & RATE_MCS_VHT_MSK) {
} else if (rate_n_flags & RATE_MCS_VHT_MSK_V1) {
rinfo->flags |= RATE_INFO_FLAGS_VHT_MCS;
rinfo->mcs = u32_get_bits(rate_n_flags,
RATE_VHT_MCS_RATE_CODE_MSK);
rinfo->nss = u32_get_bits(rate_n_flags,
RATE_VHT_MCS_NSS_MSK) + 1;
if (rate_n_flags & RATE_MCS_SGI_MSK)
if (rate_n_flags & RATE_MCS_SGI_MSK_V1)
rinfo->flags |= RATE_INFO_FLAGS_SHORT_GI;
} else if (rate_n_flags & RATE_MCS_HE_MSK) {
} else if (rate_n_flags & RATE_MCS_HE_MSK_V1) {
u32 gi_ltf = u32_get_bits(rate_n_flags,
RATE_MCS_HE_GI_LTF_MSK);
RATE_MCS_HE_GI_LTF_MSK_V1);

rinfo->flags |= RATE_INFO_FLAGS_HE_MCS;
rinfo->mcs = u32_get_bits(rate_n_flags,
RATE_VHT_MCS_RATE_CODE_MSK);
rinfo->nss = u32_get_bits(rate_n_flags,
RATE_VHT_MCS_NSS_MSK) + 1;

if (rate_n_flags & RATE_MCS_HE_106T_MSK) {
if (rate_n_flags & RATE_MCS_HE_106T_MSK_V1) {
rinfo->bw = RATE_INFO_BW_HE_RU;
rinfo->he_ru_alloc = NL80211_RATE_INFO_HE_RU_ALLOC_106;
}

switch (rate_n_flags & RATE_MCS_HE_TYPE_MSK) {
case RATE_MCS_HE_TYPE_SU:
case RATE_MCS_HE_TYPE_EXT_SU:
switch (rate_n_flags & RATE_MCS_HE_TYPE_MSK_V1) {
case RATE_MCS_HE_TYPE_SU_V1:
case RATE_MCS_HE_TYPE_EXT_SU_V1:
if (gi_ltf == 0 || gi_ltf == 1)
rinfo->he_gi = NL80211_RATE_INFO_HE_GI_0_8;
else if (gi_ltf == 2)
rinfo->he_gi = NL80211_RATE_INFO_HE_GI_1_6;
else if (rate_n_flags & RATE_MCS_SGI_MSK)
else if (rate_n_flags & RATE_MCS_SGI_MSK_V1)
rinfo->he_gi = NL80211_RATE_INFO_HE_GI_0_8;
else
rinfo->he_gi = NL80211_RATE_INFO_HE_GI_3_2;
break;
case RATE_MCS_HE_TYPE_MU:
case RATE_MCS_HE_TYPE_MU_V1:
if (gi_ltf == 0 || gi_ltf == 1)
rinfo->he_gi = NL80211_RATE_INFO_HE_GI_0_8;
else if (gi_ltf == 2)
rinfo->he_gi = NL80211_RATE_INFO_HE_GI_1_6;
else
rinfo->he_gi = NL80211_RATE_INFO_HE_GI_3_2;
break;
case RATE_MCS_HE_TYPE_TRIG:
case RATE_MCS_HE_TYPE_TRIG_V1:
if (gi_ltf == 0 || gi_ltf == 1)
rinfo->he_gi = NL80211_RATE_INFO_HE_GI_1_6;
else
Expand All @@ -4954,7 +4954,7 @@ static void iwl_mvm_set_sta_rate(u32 rate_n_flags, struct rate_info *rinfo)
if (rate_n_flags & RATE_HE_DUAL_CARRIER_MODE_MSK)
rinfo->he_dcm = 1;
} else {
switch (u32_get_bits(rate_n_flags, RATE_LEGACY_RATE_MSK)) {
switch (u32_get_bits(rate_n_flags, RATE_LEGACY_RATE_MSK_V1)) {
case IWL_RATE_1M_PLCP:
rinfo->legacy = 10;
break;
Expand Down
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