Merge tag 'mvebu-fixes-4.13-2' of git://git.infradead.org/linux-mvebu…

… into fixes

Pull "mvebu fixes for 4.13 (part 2)" from Gregory CLEMENT:

All the fixes are for ARM64 mvebu:

 - Fix the RTC interrupt on A7K/A8K which was missed when switching
   from GIC to ICU
 - Mark the A7K/A8K crypto engine as dma coherent
 - Fix the number of GPIO on south bridge on Armada 3700

* tag 'mvebu-fixes-4.13-2' of git://git.infradead.org/linux-mvebu:
  ARM64: dts: marvell: armada-37xx: Fix the number of GPIO on south bridge
  arm64: dts: marvell: mark the cp110 crypto engine as dma coherent
  arm64: dts: marvell: use ICU for the CP110 slave RTC

arch/arm64/boot/dts/marvell/armada-37xx.dtsi

@@ -219,7 +219,7 @@
 				reg = <0x18800 0x100>, <0x18C00 0x20>;
 				gpiosb: gpio {
 					#gpio-cells = <2>;
-					gpio-ranges = <&pinctrl_sb 0 0 29>;
+					gpio-ranges = <&pinctrl_sb 0 0 30>;
 					gpio-controller;
 					interrupts =
 					<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi

@@ -270,6 +270,7 @@
 				interrupt-names = "mem", "ring0", "ring1",
 				"ring2", "ring3", "eip";
 				clocks = <&cpm_clk 1 26>;
+				dma-coherent;
 			};
 		};
 

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi

@@ -64,7 +64,7 @@
 				compatible = "marvell,armada-8k-rtc";
 				reg = <0x284000 0x20>, <0x284080 0x24>;
 				reg-names = "rtc", "rtc-soc";
-				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			cps_ethernet: ethernet@0 {
@@ -261,6 +261,7 @@
 				interrupt-names = "mem", "ring0", "ring1",
 						  "ring2", "ring3", "eip";
 				clocks = <&cps_clk 1 26>;
+				dma-coherent;
 				/*
 				 * The cryptographic engine found on the cp110
 				 * master is enabled by default at the SoC