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Merge tag 'arc-4.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/…
…git/vgupta/arc Pull ARC updates from Vineet Gupta: - ARCv2 support for native 64-bit atomics using LLOCK/SCONDD instructions - Support for upcoming 3.0 release of HS38 cores - Dwarf unwindinder improvements: - enable unwinding of hand written assembler code using CFI pseudo-ops - switch to .eh_frame (as opposed to historic .debug_frame) - get rid of a bunch of adhoc band-aids in the process - Misc fixes: - perf supporting generic cache-references and cache-misses (Alexey) - default NODE_SHIFT (Noam Camus) - usage of KFLAG instruction to set IE (Yuriy) - Platforms: - Add "model" property across the DT (Alexey) - Enable MODULE_* in defconfigs * tag 'arc-4.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: [plat*] enables MODULE* ARCv2: fix local_save_flags ARC: CONFIG_NODES_SHIFT fix default values ARCv2: intc: Use kflag if STATUS32.IE must be reset ARC: .exit.* sections can be discarded in .eh_frame regime ARC: dw2 unwind: enable cfi pseudo ops in string lib ARC: dw2 unwind: add infrastructure for adding cfi pseudo ops to asm ARC: entry: make ret_from_system_call local label ARC: dw2 unwind: don't force dwarf 2 ARC: dw2 unwind: switch to .eh_frame based unwinding ARC: dw2 unwind: factor CIE specifics for .eh_frame/.debug_frame ARC: module: support R_ARC_32_PCREL relocation arc: perf: Enable generic "cache-references" and "cache-misses" events ARC: [plat-eznps] add missing atomic_fetch_xxx operations ARCv2: Implement atomic64 based on LLOCKD/SCONDD instructions ARCv2: Support dynamic peripheral address space in HS38 rel 3.0 cores ARCv2: identify HS38 rel 3.0 cores ARCv2: Add support for ZeBu Emulation platform for HS cores arc: Add "model" properly in device tree description of all boards
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Original file line number | Diff line number | Diff line change |
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/include/ "vdk_axs10x_mb.dtsi" | ||
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/ { | ||
model = "snps,vdk_archs"; | ||
compatible = "snps,axs103"; | ||
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chosen { | ||
|
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@@ -0,0 +1,69 @@ | ||
/* | ||
* Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) | ||
* | ||
* This program is free software; you can redistribute it and/or modify | ||
* it under the terms of the GNU General Public License version 2 as | ||
* published by the Free Software Foundation. | ||
*/ | ||
/dts-v1/; | ||
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/include/ "skeleton_hs.dtsi" | ||
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/ { | ||
model = "snps,zebu_hs"; | ||
compatible = "snps,zebu_hs"; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
interrupt-parent = <&core_intc>; | ||
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memory { | ||
device_type = "memory"; | ||
reg = <0x80000000 0x20000000>; /* 512 */ | ||
}; | ||
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chosen { | ||
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; | ||
}; | ||
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aliases { | ||
serial0 = &uart0; | ||
}; | ||
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fpga { | ||
compatible = "simple-bus"; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
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/* child and parent address space 1:1 mapped */ | ||
ranges; | ||
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core_clk: core_clk { | ||
#clock-cells = <0>; | ||
compatible = "fixed-clock"; | ||
clock-frequency = <50000000>; | ||
}; | ||
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core_intc: interrupt-controller { | ||
compatible = "snps,archs-intc"; | ||
interrupt-controller; | ||
#interrupt-cells = <1>; | ||
}; | ||
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uart0: serial@f0000000 { | ||
compatible = "ns8250"; | ||
reg = <0xf0000000 0x2000>; | ||
interrupts = <24>; | ||
clock-frequency = <50000000>; | ||
baud = <115200>; | ||
reg-shift = <2>; | ||
reg-io-width = <4>; | ||
no-loopback-test = <1>; | ||
}; | ||
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arcpct0: pct { | ||
compatible = "snps,archs-pct"; | ||
#interrupt-cells = <1>; | ||
interrupts = <20>; | ||
}; | ||
}; | ||
}; |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,85 @@ | ||
/* | ||
* Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) | ||
* | ||
* This program is free software; you can redistribute it and/or modify | ||
* it under the terms of the GNU General Public License version 2 as | ||
* published by the Free Software Foundation. | ||
*/ | ||
/dts-v1/; | ||
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/include/ "skeleton_hs_idu.dtsi" | ||
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/ { | ||
model = "snps,zebu_hs-smp"; | ||
compatible = "snps,zebu_hs"; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
interrupt-parent = <&core_intc>; | ||
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memory { | ||
device_type = "memory"; | ||
reg = <0x80000000 0x20000000>; /* 512 */ | ||
}; | ||
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||
chosen { | ||
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug"; | ||
}; | ||
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||
aliases { | ||
serial0 = &uart0; | ||
}; | ||
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||
fpga { | ||
compatible = "simple-bus"; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
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||
/* child and parent address space 1:1 mapped */ | ||
ranges; | ||
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core_clk: core_clk { | ||
#clock-cells = <0>; | ||
compatible = "fixed-clock"; | ||
clock-frequency = <50000000>; /* 50 MHZ */ | ||
}; | ||
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core_intc: interrupt-controller { | ||
compatible = "snps,archs-intc"; | ||
interrupt-controller; | ||
#interrupt-cells = <1>; | ||
/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */ | ||
}; | ||
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idu_intc: idu-interrupt-controller { | ||
compatible = "snps,archs-idu-intc"; | ||
interrupt-controller; | ||
interrupt-parent = <&core_intc>; | ||
/* <hwirq distribution> | ||
distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 */ | ||
#interrupt-cells = <2>; | ||
interrupts = <24 25 26 27 28 29 30 31>; | ||
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}; | ||
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uart0: serial@f0000000 { | ||
/* compatible = "ns8250"; Doesn't use FIFOs */ | ||
compatible = "ns16550a"; | ||
reg = <0xf0000000 0x2000>; | ||
interrupt-parent = <&idu_intc>; | ||
/* interrupts = <0 1>; DEST=1*/ | ||
/* interrupts = <0 2>; DEST=2*/ | ||
interrupts = <0 0>; /* RR*/ | ||
clock-frequency = <50000000>; | ||
baud = <115200>; | ||
reg-shift = <2>; | ||
reg-io-width = <4>; | ||
no-loopback-test = <1>; | ||
}; | ||
|
||
arcpct0: pct { | ||
compatible = "snps,archs-pct"; | ||
#interrupt-cells = <1>; | ||
interrupts = <20>; | ||
}; | ||
}; | ||
}; |
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