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drm/radeon: clean up active vram sizing
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If we are not able to properly initialize one of the gpu
engines for buffer paging, we limit vram to the size of
the cpu visible aperture.  We generally either use the gfx
or dma engine to do this.  Clean up the size limiting code
to only adjust the size based on what ring is selected
for buffer paging rather than making assumptions about which
engine is selected for paging.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
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Alex Deucher committed Jan 29, 2014
1 parent b9ace36 commit 50efa51
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Showing 8 changed files with 37 additions and 12 deletions.
6 changes: 6 additions & 0 deletions drivers/gpu/drm/radeon/cik.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3840,6 +3840,8 @@ static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
if (enable)
WREG32(CP_ME_CNTL, 0);
else {
if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
}
Expand Down Expand Up @@ -4038,6 +4040,10 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev)
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
return r;
}

if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);

return 0;
}

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8 changes: 6 additions & 2 deletions drivers/gpu/drm/radeon/cik_sdma.c
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Original file line number Diff line number Diff line change
Expand Up @@ -250,7 +250,9 @@ static void cik_sdma_gfx_stop(struct radeon_device *rdev)
u32 rb_cntl, reg_offset;
int i;

radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
(rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);

for (i = 0; i < 2; i++) {
if (i == 0)
Expand Down Expand Up @@ -381,7 +383,9 @@ static int cik_sdma_gfx_resume(struct radeon_device *rdev)
}
}

radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
(rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);

return 0;
}
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6 changes: 5 additions & 1 deletion drivers/gpu/drm/radeon/ni.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1390,7 +1390,8 @@ static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
if (enable)
WREG32(CP_ME_CNTL, 0);
else {
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
WREG32(SCRATCH_UMSK, 0);
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
Expand Down Expand Up @@ -1663,6 +1664,9 @@ static int cayman_cp_resume(struct radeon_device *rdev)
return r;
}

if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);

return 0;
}

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8 changes: 6 additions & 2 deletions drivers/gpu/drm/radeon/ni_dma.c
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Original file line number Diff line number Diff line change
Expand Up @@ -157,7 +157,9 @@ void cayman_dma_stop(struct radeon_device *rdev)
{
u32 rb_cntl;

radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
(rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);

/* dma0 */
rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
Expand Down Expand Up @@ -259,7 +261,9 @@ int cayman_dma_resume(struct radeon_device *rdev)
}
}

radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
(rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);

return 0;
}
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6 changes: 3 additions & 3 deletions drivers/gpu/drm/radeon/r600.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2254,7 +2254,8 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
*/
void r600_cp_stop(struct radeon_device *rdev)
{
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
WREG32(SCRATCH_UMSK, 0);
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
Expand Down Expand Up @@ -2613,8 +2614,7 @@ int r600_cp_resume(struct radeon_device *rdev)
return r;
}

/* RV7xx+ uses dma for paging */
if (rdev->family < CHIP_RV770)
if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);

return 0;
Expand Down
6 changes: 4 additions & 2 deletions drivers/gpu/drm/radeon/r600_dma.c
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Original file line number Diff line number Diff line change
Expand Up @@ -100,7 +100,8 @@ void r600_dma_stop(struct radeon_device *rdev)
{
u32 rb_cntl = RREG32(DMA_RB_CNTL);

radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);

rb_cntl &= ~DMA_RB_ENABLE;
WREG32(DMA_RB_CNTL, rb_cntl);
Expand Down Expand Up @@ -187,7 +188,8 @@ int r600_dma_resume(struct radeon_device *rdev)
return r;
}

radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);

return 0;
}
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3 changes: 2 additions & 1 deletion drivers/gpu/drm/radeon/rv770.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1071,7 +1071,8 @@ static void rv770_mc_program(struct radeon_device *rdev)
*/
void r700_cp_stop(struct radeon_device *rdev)
{
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
WREG32(SCRATCH_UMSK, 0);
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
Expand Down
6 changes: 5 additions & 1 deletion drivers/gpu/drm/radeon/si.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3249,7 +3249,8 @@ static void si_cp_enable(struct radeon_device *rdev, bool enable)
if (enable)
WREG32(CP_ME_CNTL, 0);
else {
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
WREG32(SCRATCH_UMSK, 0);
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
Expand Down Expand Up @@ -3510,6 +3511,9 @@ static int si_cp_resume(struct radeon_device *rdev)

si_enable_gui_idle_interrupt(rdev, true);

if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);

return 0;
}

Expand Down

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