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ARM: 9388/2: mm: Type-annotate all per-processor assembly routines
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Type tag the remaining per-processor assembly using the CFI
symbol macros, in addition to those that were previously tagged
for cache maintenance calls.

This will be used to finally provide proper C prototypes for
all these calls as well so that CFI can be made to work.

Tested-by: Kees Cook <keescook@chromium.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Sami Tolvanen <samitolvanen@google.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Linus Walleij authored and Russell King (Oracle) committed Apr 29, 2024
1 parent b4d20ef commit 51db13a
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Showing 26 changed files with 434 additions and 274 deletions.
24 changes: 15 additions & 9 deletions arch/arm/mm/proc-arm1020.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -57,18 +57,20 @@
/*
* cpu_arm1020_proc_init()
*/
ENTRY(cpu_arm1020_proc_init)
SYM_TYPED_FUNC_START(cpu_arm1020_proc_init)
ret lr
SYM_FUNC_END(cpu_arm1020_proc_init)

/*
* cpu_arm1020_proc_fin()
*/
ENTRY(cpu_arm1020_proc_fin)
SYM_TYPED_FUNC_START(cpu_arm1020_proc_fin)
mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches
ret lr
SYM_FUNC_END(cpu_arm1020_proc_fin)

/*
* cpu_arm1020_reset(loc)
Expand All @@ -81,7 +83,7 @@ ENTRY(cpu_arm1020_proc_fin)
*/
.align 5
.pushsection .idmap.text, "ax"
ENTRY(cpu_arm1020_reset)
SYM_TYPED_FUNC_START(cpu_arm1020_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
mcr p15, 0, ip, c7, c10, 4 @ drain WB
Expand All @@ -93,16 +95,17 @@ ENTRY(cpu_arm1020_reset)
bic ip, ip, #0x1100 @ ...i...s........
mcr p15, 0, ip, c1, c0, 0 @ ctrl register
ret r0
ENDPROC(cpu_arm1020_reset)
SYM_FUNC_END(cpu_arm1020_reset)
.popsection

/*
* cpu_arm1020_do_idle()
*/
.align 5
ENTRY(cpu_arm1020_do_idle)
SYM_TYPED_FUNC_START(cpu_arm1020_do_idle)
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
ret lr
SYM_FUNC_END(cpu_arm1020_do_idle)

/* ================================= CACHE ================================ */

Expand Down Expand Up @@ -360,7 +363,7 @@ SYM_TYPED_FUNC_START(arm1020_dma_unmap_area)
SYM_FUNC_END(arm1020_dma_unmap_area)

.align 5
ENTRY(cpu_arm1020_dcache_clean_area)
SYM_TYPED_FUNC_START(cpu_arm1020_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_DISABLE
mov ip, #0
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
Expand All @@ -370,6 +373,7 @@ ENTRY(cpu_arm1020_dcache_clean_area)
bhi 1b
#endif
ret lr
SYM_FUNC_END(cpu_arm1020_dcache_clean_area)

/* =============================== PageTable ============================== */

Expand All @@ -381,7 +385,7 @@ ENTRY(cpu_arm1020_dcache_clean_area)
* pgd: new page tables
*/
.align 5
ENTRY(cpu_arm1020_switch_mm)
SYM_TYPED_FUNC_START(cpu_arm1020_switch_mm)
#ifdef CONFIG_MMU
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, r3, c7, c10, 4
Expand Down Expand Up @@ -409,14 +413,15 @@ ENTRY(cpu_arm1020_switch_mm)
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
#endif /* CONFIG_MMU */
ret lr

SYM_FUNC_END(cpu_arm1020_switch_mm)

/*
* cpu_arm1020_set_pte(ptep, pte)
*
* Set a PTE and flush it out
*/
.align 5
ENTRY(cpu_arm1020_set_pte_ext)
SYM_TYPED_FUNC_START(cpu_arm1020_set_pte_ext)
#ifdef CONFIG_MMU
armv3_set_pte_ext
mov r0, r0
Expand All @@ -427,6 +432,7 @@ ENTRY(cpu_arm1020_set_pte_ext)
mcr p15, 0, r0, c7, c10, 4 @ drain WB
#endif /* CONFIG_MMU */
ret lr
SYM_FUNC_END(cpu_arm1020_set_pte_ext)

.type __arm1020_setup, #function
__arm1020_setup:
Expand Down
24 changes: 15 additions & 9 deletions arch/arm/mm/proc-arm1020e.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -57,18 +57,20 @@
/*
* cpu_arm1020e_proc_init()
*/
ENTRY(cpu_arm1020e_proc_init)
SYM_TYPED_FUNC_START(cpu_arm1020e_proc_init)
ret lr
SYM_FUNC_END(cpu_arm1020e_proc_init)

/*
* cpu_arm1020e_proc_fin()
*/
ENTRY(cpu_arm1020e_proc_fin)
SYM_TYPED_FUNC_START(cpu_arm1020e_proc_fin)
mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches
ret lr
SYM_FUNC_END(cpu_arm1020e_proc_fin)

/*
* cpu_arm1020e_reset(loc)
Expand All @@ -81,7 +83,7 @@ ENTRY(cpu_arm1020e_proc_fin)
*/
.align 5
.pushsection .idmap.text, "ax"
ENTRY(cpu_arm1020e_reset)
SYM_TYPED_FUNC_START(cpu_arm1020e_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
mcr p15, 0, ip, c7, c10, 4 @ drain WB
Expand All @@ -93,16 +95,17 @@ ENTRY(cpu_arm1020e_reset)
bic ip, ip, #0x1100 @ ...i...s........
mcr p15, 0, ip, c1, c0, 0 @ ctrl register
ret r0
ENDPROC(cpu_arm1020e_reset)
SYM_FUNC_END(cpu_arm1020e_reset)
.popsection

/*
* cpu_arm1020e_do_idle()
*/
.align 5
ENTRY(cpu_arm1020e_do_idle)
SYM_TYPED_FUNC_START(cpu_arm1020e_do_idle)
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
ret lr
SYM_FUNC_END(cpu_arm1020e_do_idle)

/* ================================= CACHE ================================ */

Expand Down Expand Up @@ -347,7 +350,7 @@ SYM_TYPED_FUNC_START(arm1020e_dma_unmap_area)
SYM_FUNC_END(arm1020e_dma_unmap_area)

.align 5
ENTRY(cpu_arm1020e_dcache_clean_area)
SYM_TYPED_FUNC_START(cpu_arm1020e_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_DISABLE
mov ip, #0
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
Expand All @@ -356,6 +359,7 @@ ENTRY(cpu_arm1020e_dcache_clean_area)
bhi 1b
#endif
ret lr
SYM_FUNC_END(cpu_arm1020e_dcache_clean_area)

/* =============================== PageTable ============================== */

Expand All @@ -367,7 +371,7 @@ ENTRY(cpu_arm1020e_dcache_clean_area)
* pgd: new page tables
*/
.align 5
ENTRY(cpu_arm1020e_switch_mm)
SYM_TYPED_FUNC_START(cpu_arm1020e_switch_mm)
#ifdef CONFIG_MMU
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, r3, c7, c10, 4
Expand All @@ -394,14 +398,15 @@ ENTRY(cpu_arm1020e_switch_mm)
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
#endif
ret lr

SYM_FUNC_END(cpu_arm1020e_switch_mm)

/*
* cpu_arm1020e_set_pte(ptep, pte)
*
* Set a PTE and flush it out
*/
.align 5
ENTRY(cpu_arm1020e_set_pte_ext)
SYM_TYPED_FUNC_START(cpu_arm1020e_set_pte_ext)
#ifdef CONFIG_MMU
armv3_set_pte_ext
mov r0, r0
Expand All @@ -410,6 +415,7 @@ ENTRY(cpu_arm1020e_set_pte_ext)
#endif
#endif /* CONFIG_MMU */
ret lr
SYM_FUNC_END(cpu_arm1020e_set_pte_ext)

.type __arm1020e_setup, #function
__arm1020e_setup:
Expand Down
24 changes: 15 additions & 9 deletions arch/arm/mm/proc-arm1022.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -57,18 +57,20 @@
/*
* cpu_arm1022_proc_init()
*/
ENTRY(cpu_arm1022_proc_init)
SYM_TYPED_FUNC_START(cpu_arm1022_proc_init)
ret lr
SYM_FUNC_END(cpu_arm1022_proc_init)

/*
* cpu_arm1022_proc_fin()
*/
ENTRY(cpu_arm1022_proc_fin)
SYM_TYPED_FUNC_START(cpu_arm1022_proc_fin)
mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches
ret lr
SYM_FUNC_END(cpu_arm1022_proc_fin)

/*
* cpu_arm1022_reset(loc)
Expand All @@ -81,7 +83,7 @@ ENTRY(cpu_arm1022_proc_fin)
*/
.align 5
.pushsection .idmap.text, "ax"
ENTRY(cpu_arm1022_reset)
SYM_TYPED_FUNC_START(cpu_arm1022_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
mcr p15, 0, ip, c7, c10, 4 @ drain WB
Expand All @@ -93,16 +95,17 @@ ENTRY(cpu_arm1022_reset)
bic ip, ip, #0x1100 @ ...i...s........
mcr p15, 0, ip, c1, c0, 0 @ ctrl register
ret r0
ENDPROC(cpu_arm1022_reset)
SYM_FUNC_END(cpu_arm1022_reset)
.popsection

/*
* cpu_arm1022_do_idle()
*/
.align 5
ENTRY(cpu_arm1022_do_idle)
SYM_TYPED_FUNC_START(cpu_arm1022_do_idle)
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
ret lr
SYM_FUNC_END(cpu_arm1022_do_idle)

/* ================================= CACHE ================================ */

Expand Down Expand Up @@ -346,7 +349,7 @@ SYM_TYPED_FUNC_START(arm1022_dma_unmap_area)
SYM_FUNC_END(arm1022_dma_unmap_area)

.align 5
ENTRY(cpu_arm1022_dcache_clean_area)
SYM_TYPED_FUNC_START(cpu_arm1022_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_DISABLE
mov ip, #0
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
Expand All @@ -355,6 +358,7 @@ ENTRY(cpu_arm1022_dcache_clean_area)
bhi 1b
#endif
ret lr
SYM_FUNC_END(cpu_arm1022_dcache_clean_area)

/* =============================== PageTable ============================== */

Expand All @@ -366,7 +370,7 @@ ENTRY(cpu_arm1022_dcache_clean_area)
* pgd: new page tables
*/
.align 5
ENTRY(cpu_arm1022_switch_mm)
SYM_TYPED_FUNC_START(cpu_arm1022_switch_mm)
#ifdef CONFIG_MMU
#ifndef CONFIG_CPU_DCACHE_DISABLE
mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
Expand All @@ -386,14 +390,15 @@ ENTRY(cpu_arm1022_switch_mm)
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
#endif
ret lr

SYM_FUNC_END(cpu_arm1022_switch_mm)

/*
* cpu_arm1022_set_pte_ext(ptep, pte, ext)
*
* Set a PTE and flush it out
*/
.align 5
ENTRY(cpu_arm1022_set_pte_ext)
SYM_TYPED_FUNC_START(cpu_arm1022_set_pte_ext)
#ifdef CONFIG_MMU
armv3_set_pte_ext
mov r0, r0
Expand All @@ -402,6 +407,7 @@ ENTRY(cpu_arm1022_set_pte_ext)
#endif
#endif /* CONFIG_MMU */
ret lr
SYM_FUNC_END(cpu_arm1022_set_pte_ext)

.type __arm1022_setup, #function
__arm1022_setup:
Expand Down
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