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ARM: msm: Remove pen_release usage
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pen_release is no longer required as the synchronization
is now managed by generic arm code.
This is done as suggested in https://lkml.org/lkml/2013/6/4/184

Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Rohit Vaswani authored and Kumar Gala committed Feb 4, 2014
1 parent cc60a1a commit 52b52b4
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Showing 4 changed files with 8 additions and 101 deletions.
2 changes: 1 addition & 1 deletion arch/arm/mach-msm/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)

obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_SMP) += platsmp.o

obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
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39 changes: 0 additions & 39 deletions arch/arm/mach-msm/headsmp.S

This file was deleted.

31 changes: 4 additions & 27 deletions arch/arm/mach-msm/hotplug.c
Original file line number Diff line number Diff line change
Expand Up @@ -24,33 +24,10 @@ static inline void cpu_leave_lowpower(void)

static inline void platform_do_lowpower(unsigned int cpu)
{
/* Just enter wfi for now. TODO: Properly shut off the cpu. */
for (;;) {
/*
* here's the WFI
*/
asm("wfi"
:
:
: "memory", "cc");

if (pen_release == cpu_logical_map(cpu)) {
/*
* OK, proper wakeup, we're done
*/
break;
}

/*
* getting here, means that we have come out of WFI without
* having been woken up - this shouldn't happen
*
* The trouble is, letting people know about this is not really
* possible, since we are currently running incoherently, and
* therefore cannot safely call printk() or anything else
*/
pr_debug("CPU%u: spurious wakeup call\n", cpu);
}
asm("wfi"
:
:
: "memory", "cc");
}

/*
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37 changes: 3 additions & 34 deletions arch/arm/mach-msm/platsmp.c
Original file line number Diff line number Diff line change
Expand Up @@ -12,13 +12,10 @@
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/smp.h>
#include <linux/io.h>

#include <asm/cacheflush.h>
#include <asm/cputype.h>
#include <asm/mach-types.h>
#include <asm/smp_plat.h>

#include "scm-boot.h"
Expand All @@ -28,7 +25,7 @@
#define SCSS_CPU1CORE_RESET 0xD80
#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64

extern void msm_secondary_startup(void);
extern void secondary_startup(void);

static DEFINE_SPINLOCK(boot_lock);

Expand All @@ -40,13 +37,6 @@ static inline int get_core_count(void)

static void msm_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
pen_release = -1;
smp_wmb();

/*
* Synchronise with the boot thread.
*/
Expand All @@ -57,7 +47,7 @@ static void msm_secondary_init(unsigned int cpu)
static void prepare_cold_cpu(unsigned int cpu)
{
int ret;
ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
ret = scm_set_boot_addr(virt_to_phys(secondary_startup),
SCM_FLAG_COLDBOOT_CPU1);
if (ret == 0) {
void __iomem *sc1_base_ptr;
Expand All @@ -75,7 +65,6 @@ static void prepare_cold_cpu(unsigned int cpu)

static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
static int cold_boot_done;

/* Only need to bring cpu out of reset this way once */
Expand All @@ -90,40 +79,20 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
*/
spin_lock(&boot_lock);

/*
* The secondary processor is waiting to be released from
* the holding pen - release it, then wait for it to flag
* that it has been released by resetting pen_release.
*
* Note that "pen_release" is the hardware CPU ID, whereas
* "cpu" is Linux's internal ID.
*/
pen_release = cpu_logical_map(cpu);
sync_cache_w(&pen_release);

/*
* Send the secondary CPU a soft interrupt, thereby causing
* the boot monitor to read the system wide flags register,
* and branch to the address found there.
*/
arch_send_wakeup_ipi_mask(cpumask_of(cpu));

timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
smp_rmb();
if (pen_release == -1)
break;

udelay(10);
}

/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
spin_unlock(&boot_lock);

return pen_release != -1 ? -ENOSYS : 0;
return 0;
}

/*
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