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Kernel driver gpio-i2cmux | ||
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Author: Peter Korsgaard <peter.korsgaard@barco.com> | ||
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Description | ||
----------- | ||
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gpio-i2cmux is an i2c mux driver providing access to I2C bus segments | ||
from a master I2C bus and a hardware MUX controlled through GPIO pins. | ||
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E.G.: | ||
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---------- ---------- Bus segment 1 - - - - - | ||
| | SCL/SDA | |-------------- | | | ||
| |------------| | | ||
| | | | Bus segment 2 | | | ||
| Linux | GPIO 1..N | MUX |--------------- Devices | ||
| |------------| | | | | ||
| | | | Bus segment M | ||
| | | |---------------| | | ||
---------- ---------- - - - - - | ||
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SCL/SDA of the master I2C bus is multiplexed to bus segment 1..M | ||
according to the settings of the GPIO pins 1..N. | ||
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Usage | ||
----- | ||
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gpio-i2cmux uses the platform bus, so you need to provide a struct | ||
platform_device with the platform_data pointing to a struct | ||
gpio_i2cmux_platform_data with the I2C adapter number of the master | ||
bus, the number of bus segments to create and the GPIO pins used | ||
to control it. See include/linux/gpio-i2cmux.h for details. | ||
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E.G. something like this for a MUX providing 4 bus segments | ||
controlled through 3 GPIO pins: | ||
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#include <linux/gpio-i2cmux.h> | ||
#include <linux/platform_device.h> | ||
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static const unsigned myboard_gpiomux_gpios[] = { | ||
AT91_PIN_PC26, AT91_PIN_PC25, AT91_PIN_PC24 | ||
}; | ||
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static const unsigned myboard_gpiomux_values[] = { | ||
0, 1, 2, 3 | ||
}; | ||
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static struct gpio_i2cmux_platform_data myboard_i2cmux_data = { | ||
.parent = 1, | ||
.base_nr = 2, /* optional */ | ||
.values = myboard_gpiomux_values, | ||
.n_values = ARRAY_SIZE(myboard_gpiomux_values), | ||
.gpios = myboard_gpiomux_gpios, | ||
.n_gpios = ARRAY_SIZE(myboard_gpiomux_gpios), | ||
.idle = 4, /* optional */ | ||
}; | ||
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static struct platform_device myboard_i2cmux = { | ||
.name = "gpio-i2cmux", | ||
.id = 0, | ||
.dev = { | ||
.platform_data = &myboard_i2cmux_data, | ||
}, | ||
}; |
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PPC4xx Clock Power Management (CPM) node | ||
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Required properties: | ||
- compatible : compatible list, currently only "ibm,cpm" | ||
- dcr-access-method : "native" | ||
- dcr-reg : < DCR register range > | ||
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Optional properties: | ||
- er-offset : All 4xx SoCs with a CPM controller have | ||
one of two different order for the CPM | ||
registers. Some have the CPM registers | ||
in the following order (ER,FR,SR). The | ||
others have them in the following order | ||
(SR,ER,FR). For the second case set | ||
er-offset = <1>. | ||
- unused-units : specifier consist of one cell. For each | ||
bit in the cell, the corresponding bit | ||
in CPM will be set to turn off unused | ||
devices. | ||
- idle-doze : specifier consist of one cell. For each | ||
bit in the cell, the corresponding bit | ||
in CPM will be set to turn off unused | ||
devices. This is usually just CPM[CPU]. | ||
- standby : specifier consist of one cell. For each | ||
bit in the cell, the corresponding bit | ||
in CPM will be set on standby and | ||
restored on resume. | ||
- suspend : specifier consist of one cell. For each | ||
bit in the cell, the corresponding bit | ||
in CPM will be set on suspend (mem) and | ||
restored on resume. Note, for standby | ||
and suspend the corresponding bits can | ||
be different or the same. Usually for | ||
standby only class 2 and 3 units are set. | ||
However, the interface does not care. | ||
If they are the same, the additional | ||
power saving will be seeing if support | ||
is available to put the DDR in self | ||
refresh mode and any additional power | ||
saving techniques for the specific SoC. | ||
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Example: | ||
CPM0: cpm { | ||
compatible = "ibm,cpm"; | ||
dcr-access-method = "native"; | ||
dcr-reg = <0x160 0x003>; | ||
er-offset = <0>; | ||
unused-units = <0x00000100>; | ||
idle-doze = <0x02000000>; | ||
standby = <0xfeff0000>; | ||
suspend = <0xfeff791d>; | ||
}; |
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