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drm/i915/dsi: account for DSC in horizontal timings
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When DSC is enabled, we need to adjust the horizontal timings to account
for the compressed (and therefore reduced) link speed.

The compressed frequency ratio simplifies down to the ratio between
compressed and non-compressed bpp.

Bspec: 49263
Suggested-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/fecebdc2719dd0c78eaf8f4d3225bb185956d7db.1575974743.git.jani.nikula@intel.com
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Jani Nikula committed Dec 11, 2019
1 parent 38b8988 commit 53693f0
Showing 1 changed file with 19 additions and 5 deletions.
24 changes: 19 additions & 5 deletions drivers/gpu/drm/i915/display/icl_dsi.c
Original file line number Diff line number Diff line change
Expand Up @@ -785,24 +785,38 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,

static void
gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
&crtc_state->hw.adjusted_mode;
enum port port;
enum transcoder dsi_trans;
/* horizontal timings */
u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
u16 hback_porch;
/* vertical timings */
u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
int mul = 1, div = 1;

/*
* Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
* for slower link speed if DSC is enabled.
*
* The compression frequency ratio is the ratio between compressed and
* non-compressed link speeds, and simplifies down to the ratio between
* compressed and non-compressed bpp.
*/
if (crtc_state->dsc.compression_enable) {
mul = crtc_state->dsc.compressed_bpp;
div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
}

hactive = adjusted_mode->crtc_hdisplay;
htotal = adjusted_mode->crtc_htotal;
hsync_start = adjusted_mode->crtc_hsync_start;
hsync_end = adjusted_mode->crtc_hsync_end;
htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
hsync_size = hsync_end - hsync_start;
hback_porch = (adjusted_mode->crtc_htotal -
adjusted_mode->crtc_hsync_end);
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