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staging: tidspbridge: drop const from custom mmu implementation
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Custom mmu functions receive a 'const void __iomem *', all the
callers pass a 'void __iomem *', so drop the const to fix the
warnings like:

warning: passing argument 2 of '__raw_writel' discards qualifiers from pointer target type
../io.h:88: note: expected 'volatile void *' but argument is of type 'const void *'

Signed-off-by: Omar Ramirez Luna <omar.ramirez@copitl.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Omar Ramirez Luna authored and Greg Kroah-Hartman committed Oct 24, 2012
1 parent b8cac0b commit 53e3e3f
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Showing 2 changed files with 34 additions and 34 deletions.
40 changes: 20 additions & 20 deletions drivers/staging/tidspbridge/hw/hw_mmu.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address);
* INPUTS:
*
* Identifier : base_address
* TypE : const u32
* Type : void __iomem *
* Description : Base Address of instance of MMU module
*
* Identifier : page_sz
Expand Down Expand Up @@ -112,7 +112,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address);
*
* METHOD: : Check the Input parameters and set the CAM entry.
*/
static hw_status mmu_set_cam_entry(const void __iomem *base_address,
static hw_status mmu_set_cam_entry(void __iomem *base_address,
const u32 page_sz,
const u32 preserved_bit,
const u32 valid_bit,
Expand All @@ -124,7 +124,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address,
* INPUTS:
*
* Identifier : base_address
* Type : const u32
* Type : void __iomem *
* Description : Base Address of instance of MMU module
*
* Identifier : physical_addr
Expand Down Expand Up @@ -157,15 +157,15 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address,
*
* METHOD: : Check the Input parameters and set the RAM entry.
*/
static hw_status mmu_set_ram_entry(const void __iomem *base_address,
static hw_status mmu_set_ram_entry(void __iomem *base_address,
const u32 physical_addr,
enum hw_endianism_t endianism,
enum hw_element_size_t element_size,
enum hw_mmu_mixed_size_t mixed_size);

/* HW FUNCTIONS */

hw_status hw_mmu_enable(const void __iomem *base_address)
hw_status hw_mmu_enable(void __iomem *base_address)
{
hw_status status = 0;

Expand All @@ -174,7 +174,7 @@ hw_status hw_mmu_enable(const void __iomem *base_address)
return status;
}

hw_status hw_mmu_disable(const void __iomem *base_address)
hw_status hw_mmu_disable(void __iomem *base_address)
{
hw_status status = 0;

Expand All @@ -183,7 +183,7 @@ hw_status hw_mmu_disable(const void __iomem *base_address)
return status;
}

hw_status hw_mmu_num_locked_set(const void __iomem *base_address,
hw_status hw_mmu_num_locked_set(void __iomem *base_address,
u32 num_locked_entries)
{
hw_status status = 0;
Expand All @@ -193,7 +193,7 @@ hw_status hw_mmu_num_locked_set(const void __iomem *base_address,
return status;
}

hw_status hw_mmu_victim_num_set(const void __iomem *base_address,
hw_status hw_mmu_victim_num_set(void __iomem *base_address,
u32 victim_entry_num)
{
hw_status status = 0;
Expand All @@ -203,7 +203,7 @@ hw_status hw_mmu_victim_num_set(const void __iomem *base_address,
return status;
}

hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irq_mask)
hw_status hw_mmu_event_ack(void __iomem *base_address, u32 irq_mask)
{
hw_status status = 0;

Expand All @@ -212,7 +212,7 @@ hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irq_mask)
return status;
}

hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irq_mask)
hw_status hw_mmu_event_disable(void __iomem *base_address, u32 irq_mask)
{
hw_status status = 0;
u32 irq_reg;
Expand All @@ -224,7 +224,7 @@ hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irq_mask)
return status;
}

hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irq_mask)
hw_status hw_mmu_event_enable(void __iomem *base_address, u32 irq_mask)
{
hw_status status = 0;
u32 irq_reg;
Expand All @@ -236,7 +236,7 @@ hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irq_mask)
return status;
}

hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irq_mask)
hw_status hw_mmu_event_status(void __iomem *base_address, u32 *irq_mask)
{
hw_status status = 0;

Expand All @@ -245,7 +245,7 @@ hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irq_mask)
return status;
}

hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr)
hw_status hw_mmu_fault_addr_read(void __iomem *base_address, u32 *addr)
{
hw_status status = 0;

Expand All @@ -255,7 +255,7 @@ hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr)
return status;
}

hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 ttb_phys_addr)
hw_status hw_mmu_ttb_set(void __iomem *base_address, u32 ttb_phys_addr)
{
hw_status status = 0;
u32 load_ttb;
Expand All @@ -267,7 +267,7 @@ hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 ttb_phys_addr)
return status;
}

hw_status hw_mmu_twl_enable(const void __iomem *base_address)
hw_status hw_mmu_twl_enable(void __iomem *base_address)
{
hw_status status = 0;

Expand All @@ -276,7 +276,7 @@ hw_status hw_mmu_twl_enable(const void __iomem *base_address)
return status;
}

hw_status hw_mmu_twl_disable(const void __iomem *base_address)
hw_status hw_mmu_twl_disable(void __iomem *base_address)
{
hw_status status = 0;

Expand Down Expand Up @@ -323,7 +323,7 @@ hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtual_addr,
return status;
}

hw_status hw_mmu_tlb_add(const void __iomem *base_address,
hw_status hw_mmu_tlb_add(void __iomem *base_address,
u32 physical_addr,
u32 virtual_addr,
u32 page_sz,
Expand Down Expand Up @@ -516,7 +516,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address)
}

/* mmu_set_cam_entry */
static hw_status mmu_set_cam_entry(const void __iomem *base_address,
static hw_status mmu_set_cam_entry(void __iomem *base_address,
const u32 page_sz,
const u32 preserved_bit,
const u32 valid_bit,
Expand All @@ -536,7 +536,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address,
}

/* mmu_set_ram_entry */
static hw_status mmu_set_ram_entry(const void __iomem *base_address,
static hw_status mmu_set_ram_entry(void __iomem *base_address,
const u32 physical_addr,
enum hw_endianism_t endianism,
enum hw_element_size_t element_size,
Expand All @@ -556,7 +556,7 @@ static hw_status mmu_set_ram_entry(const void __iomem *base_address,

}

void hw_mmu_tlb_flush_all(const void __iomem *base)
void hw_mmu_tlb_flush_all(void __iomem *base)
{
__raw_writel(1, base + MMU_GFLUSH);
}
28 changes: 14 additions & 14 deletions drivers/staging/tidspbridge/hw/hw_mmu.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,44 +42,44 @@ struct hw_mmu_map_attrs_t {
bool donotlockmpupage;
};

extern hw_status hw_mmu_enable(const void __iomem *base_address);
extern hw_status hw_mmu_enable(void __iomem *base_address);

extern hw_status hw_mmu_disable(const void __iomem *base_address);
extern hw_status hw_mmu_disable(void __iomem *base_address);

extern hw_status hw_mmu_num_locked_set(const void __iomem *base_address,
extern hw_status hw_mmu_num_locked_set(void __iomem *base_address,
u32 num_locked_entries);

extern hw_status hw_mmu_victim_num_set(const void __iomem *base_address,
extern hw_status hw_mmu_victim_num_set(void __iomem *base_address,
u32 victim_entry_num);

/* For MMU faults */
extern hw_status hw_mmu_event_ack(const void __iomem *base_address,
extern hw_status hw_mmu_event_ack(void __iomem *base_address,
u32 irq_mask);

extern hw_status hw_mmu_event_disable(const void __iomem *base_address,
extern hw_status hw_mmu_event_disable(void __iomem *base_address,
u32 irq_mask);

extern hw_status hw_mmu_event_enable(const void __iomem *base_address,
extern hw_status hw_mmu_event_enable(void __iomem *base_address,
u32 irq_mask);

extern hw_status hw_mmu_event_status(const void __iomem *base_address,
extern hw_status hw_mmu_event_status(void __iomem *base_address,
u32 *irq_mask);

extern hw_status hw_mmu_fault_addr_read(const void __iomem *base_address,
extern hw_status hw_mmu_fault_addr_read(void __iomem *base_address,
u32 *addr);

/* Set the TT base address */
extern hw_status hw_mmu_ttb_set(const void __iomem *base_address,
extern hw_status hw_mmu_ttb_set(void __iomem *base_address,
u32 ttb_phys_addr);

extern hw_status hw_mmu_twl_enable(const void __iomem *base_address);
extern hw_status hw_mmu_twl_enable(void __iomem *base_address);

extern hw_status hw_mmu_twl_disable(const void __iomem *base_address);
extern hw_status hw_mmu_twl_disable(void __iomem *base_address);

extern hw_status hw_mmu_tlb_flush(const void __iomem *base_address,
u32 virtual_addr, u32 page_sz);

extern hw_status hw_mmu_tlb_add(const void __iomem *base_address,
extern hw_status hw_mmu_tlb_add(void __iomem *base_address,
u32 physical_addr,
u32 virtual_addr,
u32 page_sz,
Expand All @@ -97,7 +97,7 @@ extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va,
extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va,
u32 virtual_addr, u32 page_size);

void hw_mmu_tlb_flush_all(const void __iomem *base);
void hw_mmu_tlb_flush_all(void __iomem *base);

static inline u32 hw_mmu_pte_addr_l1(u32 l1_base, u32 va)
{
Expand Down

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