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net: atlantic: always use random TC-queue mapping for TX on A2.
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This patch changes the TC-queue mapping mechanism used on A2.
Configure the A2 HW in such a way that we can keep queue index mapping
exactly as it was on A1.

Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Mark Starovoytov authored and David S. Miller committed May 22, 2020
1 parent 14ef766 commit 5479e84
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Showing 4 changed files with 72 additions and 11 deletions.
31 changes: 22 additions & 9 deletions drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -95,7 +95,10 @@ static int hw_atl2_hw_queue_to_tc_map_set(struct aq_hw_s *self)
struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
unsigned int tcs, q_per_tc;
unsigned int tc, q;
u32 value = 0;
u32 rx_map = 0;
u32 tx_map = 0;

hw_atl2_tpb_tx_tc_q_rand_map_en_set(self, 1U);

switch (cfg->tc_mode) {
case AQ_TC_MODE_8TCS:
Expand All @@ -113,14 +116,24 @@ static int hw_atl2_hw_queue_to_tc_map_set(struct aq_hw_s *self)
for (tc = 0; tc != tcs; tc++) {
unsigned int tc_q_offset = tc * q_per_tc;

for (q = tc_q_offset; q != tc_q_offset + q_per_tc; q++)
value |= tc << HW_ATL2_RX_Q_TC_MAP_SHIFT(q);
for (q = tc_q_offset; q != tc_q_offset + q_per_tc; q++) {
rx_map |= tc << HW_ATL2_RX_Q_TC_MAP_SHIFT(q);
if (HW_ATL2_RX_Q_TC_MAP_ADR(q) !=
HW_ATL2_RX_Q_TC_MAP_ADR(q + 1)) {
aq_hw_write_reg(self,
HW_ATL2_RX_Q_TC_MAP_ADR(q),
rx_map);
rx_map = 0;
}

if (HW_ATL2_RX_Q_TC_MAP_ADR(q) !=
HW_ATL2_RX_Q_TC_MAP_ADR(q - 1)) {
aq_hw_write_reg(self, HW_ATL2_RX_Q_TC_MAP_ADR(q - 1),
value);
value = 0;
tx_map |= tc << HW_ATL2_TX_Q_TC_MAP_SHIFT(q);
if (HW_ATL2_TX_Q_TC_MAP_ADR(q) !=
HW_ATL2_TX_Q_TC_MAP_ADR(q + 1)) {
aq_hw_write_reg(self,
HW_ATL2_TX_Q_TC_MAP_ADR(q),
tx_map);
tx_map = 0;
}
}
}

Expand Down Expand Up @@ -181,7 +194,7 @@ static int hw_atl2_hw_qos_set(struct aq_hw_s *self)
hw_atl_rpf_rpb_user_priority_tc_map_set(self, prio,
cfg->prio_tc_map[prio]);

/* ATL2 Apply legacy ring to TC mapping */
/* ATL2 Apply ring to TC mapping */
hw_atl2_hw_queue_to_tc_map_set(self);

return aq_hw_err_from_flags(self);
Expand Down
9 changes: 9 additions & 0 deletions drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c
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Original file line number Diff line number Diff line change
Expand Up @@ -68,6 +68,15 @@ void hw_atl2_rpf_vlan_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter)

/* TX */

void hw_atl2_tpb_tx_tc_q_rand_map_en_set(struct aq_hw_s *aq_hw,
const u32 tc_q_rand_map_en)
{
aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_ADR,
HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_MSK,
HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_SHIFT,
tc_q_rand_map_en);
}

void hw_atl2_tpb_tx_buf_clk_gate_en_set(struct aq_hw_s *aq_hw, u32 clk_gate_en)
{
aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_ADR,
Expand Down
4 changes: 4 additions & 0 deletions drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h
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Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,10 @@ void hw_atl2_new_rpf_rss_redir_set(struct aq_hw_s *aq_hw, u32 tc, u32 index,
/* Set VLAN filter tag */
void hw_atl2_rpf_vlan_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter);

/* set tx random TC-queue mapping enable bit */
void hw_atl2_tpb_tx_tc_q_rand_map_en_set(struct aq_hw_s *aq_hw,
const u32 tc_q_rand_map_en);

/* set tx buffer clock gate enable */
void hw_atl2_tpb_tx_buf_clk_gate_en_set(struct aq_hw_s *aq_hw, u32 clk_gate_en);

Expand Down
39 changes: 37 additions & 2 deletions drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h
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Original file line number Diff line number Diff line change
Expand Up @@ -132,6 +132,24 @@
/* Default value of bitfield rx_q{Q}_tc_map[2:0] */
#define HW_ATL2_RX_Q_TC_MAP_DEFAULT 0x0

/* tx tx_tc_q_rand_map_en bitfield definitions
* preprocessor definitions for the bitfield "tx_tc_q_rand_map_en".
* port="pif_tpb_tx_tc_q_rand_map_en_i"
*/

/* register address for bitfield tx_tc_q_rand_map_en */
#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_ADR 0x00007900
/* bitmask for bitfield tx_tc_q_rand_map_en */
#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_MSK 0x00000200
/* inverted bitmask for bitfield tx_tc_q_rand_map_en */
#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_MSKN 0xFFFFFDFF
/* lower bit position of bitfield tx_tc_q_rand_map_en */
#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_SHIFT 9
/* width of bitfield tx_tc_q_rand_map_en */
#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_WIDTH 1
/* default value of bitfield tx_tc_q_rand_map_en */
#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_DEFAULT 0x0

/* tx tx_buffer_clk_gate_en bitfield definitions
* preprocessor definitions for the bitfield "tx_buffer_clk_gate_en".
* port="pif_tpb_tx_buffer_clk_gate_en_i"
Expand All @@ -150,8 +168,25 @@
/* default value of bitfield tx_buffer_clk_gate_en */
#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_DEFAULT 0x0

/* tx data_tc{t}_credit_max[b:0] bitfield definitions
* preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]".
/* tx tx_q_tc_map{q} bitfield definitions
* preprocessor definitions for the bitfield "tx_q_tc_map{q}".
* parameter: queue {q} | bit-level stride | range [0, 31]
* port="pif_tpb_tx_q_tc_map0_i[2:0]"
*/

/* register address for bitfield tx_q_tc_map{q} */
#define HW_ATL2_TX_Q_TC_MAP_ADR(queue) \
(((queue) < 32) ? 0x0000799C + ((queue) / 4) * 4 : 0)
/* lower bit position of bitfield tx_q_tc_map{q} */
#define HW_ATL2_TX_Q_TC_MAP_SHIFT(queue) \
(((queue) < 32) ? ((queue) * 8) % 32 : 0)
/* width of bitfield tx_q_tc_map{q} */
#define HW_ATL2_TX_Q_TC_MAP_WIDTH 3
/* default value of bitfield tx_q_tc_map{q} */
#define HW_ATL2_TX_Q_TC_MAP_DEFAULT 0x0

/* tx data_tc{t}_credit_max[f:0] bitfield definitions
* preprocessor definitions for the bitfield "data_tc{t}_credit_max[f:0]".
* parameter: tc {t} | stride size 0x4 | range [0, 7]
* port="pif_tps_data_tc0_credit_max_i[11:0]"
*/
Expand Down

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