Revert "drm/i915/guc: Add delay to disable scheduling after pin count…

… goes to zero"

This reverts commit 6a07990.

Everything in CI using GuC is now timing out[1], and killing the machine
with this change (perhaps a deadlock?). CI was recently on fire due to
some changes coming in from -rc1, so likely the pre-merge CI results for
this series were invalid? For now just revert, unless GuC experts
already have a fix in mind.

[1] https://intel-gfx-ci.01.org/tree/drm-tip/index.html?

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220819123904.913750-1-matthew.auld@intel.com

drivers/gpu/drm/i915/gem/i915_gem_context.c

@@ -1454,7 +1454,7 @@ static void engines_idle_release(struct i915_gem_context *ctx,
 		int err;
 
 		/* serialises with execbuf */
-		intel_context_close(ce);
+		set_bit(CONTEXT_CLOSED_BIT, &ce->flags);
 		if (!intel_context_pin_if_active(ce))
 			continue;
 

drivers/gpu/drm/i915/gt/intel_context.h

@@ -276,14 +276,6 @@ static inline bool intel_context_is_barrier(const struct intel_context *ce)
 	return test_bit(CONTEXT_BARRIER_BIT, &ce->flags);
 }
 
-static inline void intel_context_close(struct intel_context *ce)
-{
-	set_bit(CONTEXT_CLOSED_BIT, &ce->flags);
-
-	if (ce->ops->close)
-		ce->ops->close(ce);
-}
-
 static inline bool intel_context_is_closed(const struct intel_context *ce)
 {
 	return test_bit(CONTEXT_CLOSED_BIT, &ce->flags);

drivers/gpu/drm/i915/gt/intel_context_types.h

@@ -43,8 +43,6 @@ struct intel_context_ops {
 	void (*revoke)(struct intel_context *ce, struct i915_request *rq,
 		       unsigned int preempt_timeout_ms);
 
-	void (*close)(struct intel_context *ce);
-
 	int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void **vaddr);
 	int (*pin)(struct intel_context *ce, void *vaddr);
 	void (*unpin)(struct intel_context *ce);
@@ -210,11 +208,6 @@ struct intel_context {
 		 * each priority bucket
 		 */
 		u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
-		/**
-		 * @sched_disable_delay: worker to disable scheduling on this
-		 * context
-		 */
-		struct delayed_work sched_disable_delay;
 	} guc_state;
 
 	struct {

drivers/gpu/drm/i915/gt/uc/intel_guc.h

@@ -112,10 +112,6 @@ struct intel_guc {
 		 * refs
 		 */
 		struct list_head guc_id_list;
-		/**
-		 * @guc_ids_in_use: Number single-lrc guc_ids in use
-		 */
-		u16 guc_ids_in_use;
 		/**
 		 * @destroyed_contexts: list of contexts waiting to be destroyed
 		 * (deregistered with the GuC)
@@ -136,16 +132,6 @@ struct intel_guc {
 		 * @reset_fail_mask: mask of engines that failed to reset
 		 */
 		intel_engine_mask_t reset_fail_mask;
-		/**
-		 * @sched_disable_delay_ms: schedule disable delay, in ms, for
-		 * contexts
-		 */
-		u64 sched_disable_delay_ms;
-		/**
-		 * @sched_disable_gucid_threshold: threshold of min remaining available
-		 * guc_ids before we start bypassing the schedule disable delay
-		 */
-		int sched_disable_gucid_threshold;
 	} submission_state;
 
 	/**
@@ -475,10 +461,9 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc);
 void intel_guc_submission_cancel_requests(struct intel_guc *guc);
 
 void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p);
-void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p);
 
 void intel_guc_write_barrier(struct intel_guc *guc);
 
-int intel_guc_sched_disable_gucid_threshold_max(struct intel_guc *guc);
+void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p);
 
 #endif

drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c

@@ -71,72 +71,12 @@ static bool intel_eval_slpc_support(void *data)
 	return intel_guc_slpc_is_used(guc);
 }
 
-static int guc_sched_disable_delay_ms_get(void *data, u64 *val)
-{
-	struct intel_guc *guc = data;
-
-	if (!intel_guc_submission_is_used(guc))
-		return -ENODEV;
-
-	*val = guc->submission_state.sched_disable_delay_ms;
-
-	return 0;
-}
-
-static int guc_sched_disable_delay_ms_set(void *data, u64 val)
-{
-	struct intel_guc *guc = data;
-
-	if (!intel_guc_submission_is_used(guc))
-		return -ENODEV;
-
-	guc->submission_state.sched_disable_delay_ms = val;
-
-	return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(guc_sched_disable_delay_ms_fops,
-			guc_sched_disable_delay_ms_get,
-			guc_sched_disable_delay_ms_set, "%lld\n");
-
-static int guc_sched_disable_gucid_threshold_get(void *data, u64 *val)
-{
-	struct intel_guc *guc = data;
-
-	if (!intel_guc_submission_is_used(guc))
-		return -ENODEV;
-
-	*val = guc->submission_state.sched_disable_gucid_threshold;
-	return 0;
-}
-
-static int guc_sched_disable_gucid_threshold_set(void *data, u64 val)
-{
-	struct intel_guc *guc = data;
-
-	if (!intel_guc_submission_is_used(guc))
-		return -ENODEV;
-
-	if (val > intel_guc_sched_disable_gucid_threshold_max(guc))
-		guc->submission_state.sched_disable_gucid_threshold =
-			intel_guc_sched_disable_gucid_threshold_max(guc);
-	else
-		guc->submission_state.sched_disable_gucid_threshold = val;
-
-	return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(guc_sched_disable_gucid_threshold_fops,
-			guc_sched_disable_gucid_threshold_get,
-			guc_sched_disable_gucid_threshold_set, "%lld\n");
-
 void intel_guc_debugfs_register(struct intel_guc *guc, struct dentry *root)
 {
 	static const struct intel_gt_debugfs_file files[] = {
 		{ "guc_info", &guc_info_fops, NULL },
 		{ "guc_registered_contexts", &guc_registered_contexts_fops, NULL },
 		{ "guc_slpc_info", &guc_slpc_info_fops, &intel_eval_slpc_support},
-		{ "guc_sched_disable_delay_ms", &guc_sched_disable_delay_ms_fops, NULL },
-		{ "guc_sched_disable_gucid_threshold", &guc_sched_disable_gucid_threshold_fops,
-		   NULL },
 	};
 
 	if (!intel_guc_is_supported(guc))