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ARC: intc: split into ARCompact ISA specific, common bits
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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Vineet Gupta
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Jun 19, 2015
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,181 @@ | ||
| /* | ||
| * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) | ||
| * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| */ | ||
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| #ifndef __ASM_IRQFLAGS_ARCOMPACT_H | ||
| #define __ASM_IRQFLAGS_ARCOMPACT_H | ||
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| /* vineetg: March 2010 : local_irq_save( ) optimisation | ||
| * -Remove explicit mov of current status32 into reg, that is not needed | ||
| * -Use BIC insn instead of INVERTED + AND | ||
| * -Conditionally disable interrupts (if they are not enabled, don't disable) | ||
| */ | ||
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| #include <asm/arcregs.h> | ||
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| /* status32 Reg bits related to Interrupt Handling */ | ||
| #define STATUS_E1_BIT 1 /* Int 1 enable */ | ||
| #define STATUS_E2_BIT 2 /* Int 2 enable */ | ||
| #define STATUS_A1_BIT 3 /* Int 1 active */ | ||
| #define STATUS_A2_BIT 4 /* Int 2 active */ | ||
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| #define STATUS_E1_MASK (1<<STATUS_E1_BIT) | ||
| #define STATUS_E2_MASK (1<<STATUS_E2_BIT) | ||
| #define STATUS_A1_MASK (1<<STATUS_A1_BIT) | ||
| #define STATUS_A2_MASK (1<<STATUS_A2_BIT) | ||
| #define STATUS_IE_MASK (STATUS_E1_MASK | STATUS_E2_MASK) | ||
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| /* Other Interrupt Handling related Aux regs */ | ||
| #define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */ | ||
| #define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */ | ||
| #define AUX_IRQ_LV12 0x43 /* interrupt level register */ | ||
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| #define AUX_IENABLE 0x40c | ||
| #define AUX_ITRIGGER 0x40d | ||
| #define AUX_IPULSE 0x415 | ||
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| #ifndef __ASSEMBLY__ | ||
|
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| /****************************************************************** | ||
| * IRQ Control Macros | ||
| * | ||
| * All of them have "memory" clobber (compiler barrier) which is needed to | ||
| * ensure that LD/ST requiring irq safetly (R-M-W when LLSC is not available) | ||
| * are redone after IRQs are re-enabled (and gcc doesn't reuse stale register) | ||
| * | ||
| * Noted at the time of Abilis Timer List corruption | ||
| * Orig Bug + Rejected solution : https://lkml.org/lkml/2013/3/29/67 | ||
| * Reasoning : https://lkml.org/lkml/2013/4/8/15 | ||
| * | ||
| ******************************************************************/ | ||
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| /* | ||
| * Save IRQ state and disable IRQs | ||
| */ | ||
| static inline long arch_local_irq_save(void) | ||
| { | ||
| unsigned long temp, flags; | ||
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| __asm__ __volatile__( | ||
| " lr %1, [status32] \n" | ||
| " bic %0, %1, %2 \n" | ||
| " and.f 0, %1, %2 \n" | ||
| " flag.nz %0 \n" | ||
| : "=r"(temp), "=r"(flags) | ||
| : "n"((STATUS_E1_MASK | STATUS_E2_MASK)) | ||
| : "memory", "cc"); | ||
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| return flags; | ||
| } | ||
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| /* | ||
| * restore saved IRQ state | ||
| */ | ||
| static inline void arch_local_irq_restore(unsigned long flags) | ||
| { | ||
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| __asm__ __volatile__( | ||
| " flag %0 \n" | ||
| : | ||
| : "r"(flags) | ||
| : "memory"); | ||
| } | ||
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| /* | ||
| * Unconditionally Enable IRQs | ||
| */ | ||
| extern void arch_local_irq_enable(void); | ||
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| /* | ||
| * Unconditionally Disable IRQs | ||
| */ | ||
| static inline void arch_local_irq_disable(void) | ||
| { | ||
| unsigned long temp; | ||
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| __asm__ __volatile__( | ||
| " lr %0, [status32] \n" | ||
| " and %0, %0, %1 \n" | ||
| " flag %0 \n" | ||
| : "=&r"(temp) | ||
| : "n"(~(STATUS_E1_MASK | STATUS_E2_MASK)) | ||
| : "memory"); | ||
| } | ||
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| /* | ||
| * save IRQ state | ||
| */ | ||
| static inline long arch_local_save_flags(void) | ||
| { | ||
| unsigned long temp; | ||
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| __asm__ __volatile__( | ||
| " lr %0, [status32] \n" | ||
| : "=&r"(temp) | ||
| : | ||
| : "memory"); | ||
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| return temp; | ||
| } | ||
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| /* | ||
| * Query IRQ state | ||
| */ | ||
| static inline int arch_irqs_disabled_flags(unsigned long flags) | ||
| { | ||
| return !(flags & (STATUS_E1_MASK | ||
| #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS | ||
| | STATUS_E2_MASK | ||
| #endif | ||
| )); | ||
| } | ||
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| static inline int arch_irqs_disabled(void) | ||
| { | ||
| return arch_irqs_disabled_flags(arch_local_save_flags()); | ||
| } | ||
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| #else | ||
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| #ifdef CONFIG_TRACE_IRQFLAGS | ||
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| .macro TRACE_ASM_IRQ_DISABLE | ||
| bl trace_hardirqs_off | ||
| .endm | ||
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| .macro TRACE_ASM_IRQ_ENABLE | ||
| bl trace_hardirqs_on | ||
| .endm | ||
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| #else | ||
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| .macro TRACE_ASM_IRQ_DISABLE | ||
| .endm | ||
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| .macro TRACE_ASM_IRQ_ENABLE | ||
| .endm | ||
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| #endif | ||
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| .macro IRQ_DISABLE scratch | ||
| lr \scratch, [status32] | ||
| bic \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK) | ||
| flag \scratch | ||
| TRACE_ASM_IRQ_DISABLE | ||
| .endm | ||
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| .macro IRQ_ENABLE scratch | ||
| lr \scratch, [status32] | ||
| or \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK) | ||
| flag \scratch | ||
| TRACE_ASM_IRQ_ENABLE | ||
| .endm | ||
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| #endif /* __ASSEMBLY__ */ | ||
|
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| #endif |
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