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drm/nouveau/kms/nv140-: Use hard-coded wndws or core channel for CRC …
…channel
Originally it was assumed based on Nvidia's open-gpu-docs and testing that
NVDisplay required that at least one wndw which belongs to a given head to
be used as the controlling channel
(NVC37D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL) in order for CRC capture
to function. While this is the case on Volta, Turing actually adds the
ability to instead use the core channel as the controlling channel. For
Turing this is quite useful, as it means that we can always default to the
core channel as the controlling channel and we don't need to be concerned
about ensuring we have at least one wndw channel owned by a head with CRC
output enabled. While Volta lacks this ability, Volta conveniently also
lacks flexible wndw mapping - meaning that we can always rely on each head
having four wndw channels mapped to it regardless of the atomic state.
So, simply use the hard-coded wndw mappings we're guaranteed to have on
Volta as the controlling channel, and use the core channel as the
controlling channel for Turing+. As a result this also renders the plane
ownership logic in nv50_crc_atomic_check() unnessecary, which gives us one
less thing to implement when we get support for flexible wndw mapping. We
also can entirely drop the wndw parameter from our set_src callbacks, and
the atomic state.
v2 (Karol): put prackets around complex macro definition
removed spaces before :32 in structs
Cc: Martin Peres <martin.peres@free.fr>
Cc: Jeremy Cline <jcline@redhat.com>
Cc: Simon Ser <contact@emersion.fr>
Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Link: https://gitlab.freedesktop.org/drm/nouveau/-/merge_requests/10- Loading branch information
Lyude Paul
authored and
Karol Herbst
committed
Nov 12, 2021
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,40 @@ | ||
| /* SPDX-License-Identifier: MIT */ | ||
|
|
||
| #ifndef __CRCC37D_H__ | ||
| #define __CRCC37D_H__ | ||
|
|
||
| #include <linux/types.h> | ||
|
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||
| #include "crc.h" | ||
|
|
||
| #define CRCC37D_MAX_ENTRIES 2047 | ||
| #define CRCC37D_FLIP_THRESHOLD (CRCC37D_MAX_ENTRIES - 30) | ||
|
|
||
| struct crcc37d_notifier { | ||
| u32 status; | ||
|
|
||
| /* reserved */ | ||
| u32:32; | ||
| u32:32; | ||
| u32:32; | ||
| u32:32; | ||
| u32:32; | ||
| u32:32; | ||
| u32:32; | ||
|
|
||
| struct crcc37d_entry { | ||
| u32 status[2]; | ||
| u32:32; /* reserved */ | ||
| u32 compositor_crc; | ||
| u32 rg_crc; | ||
| u32 output_crc[2]; | ||
| u32:32; /* reserved */ | ||
| } entries[CRCC37D_MAX_ENTRIES]; | ||
| } __packed; | ||
|
|
||
| int crcc37d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx); | ||
| u32 crcc37d_get_entry(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx, | ||
| enum nv50_crc_source source, int idx); | ||
| bool crcc37d_ctx_finished(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx); | ||
|
|
||
| #endif /* !__CRCC37D_H__ */ |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,58 @@ | ||
| // SPDX-License-Identifier: MIT | ||
|
|
||
| #include "crc.h" | ||
| #include "crcc37d.h" | ||
| #include "core.h" | ||
| #include "disp.h" | ||
| #include "head.h" | ||
|
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| #include <nvif/pushc37b.h> | ||
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| #include <nvhw/class/clc57d.h> | ||
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| static int crcc57d_set_src(struct nv50_head *head, int or, enum nv50_crc_source_type source, | ||
| struct nv50_crc_notifier_ctx *ctx) | ||
| { | ||
| struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; | ||
| const int i = head->base.index; | ||
| u32 crc_args = NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) | | ||
| NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) | | ||
| NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, SECONDARY_CRC, NONE) | | ||
| NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE); | ||
| int ret; | ||
|
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||
| switch (source) { | ||
| case NV50_CRC_SOURCE_TYPE_SOR: | ||
| crc_args |= NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SOR(or)); | ||
| break; | ||
| case NV50_CRC_SOURCE_TYPE_SF: | ||
| crc_args |= NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SF); | ||
| break; | ||
| default: | ||
| break; | ||
| } | ||
|
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| ret = PUSH_WAIT(push, 4); | ||
| if (ret) | ||
| return ret; | ||
|
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||
| if (source) { | ||
| PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle); | ||
| PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), crc_args); | ||
| } else { | ||
| PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), 0); | ||
| PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), 0); | ||
| } | ||
|
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| return 0; | ||
| } | ||
|
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| const struct nv50_crc_func crcc57d = { | ||
| .set_src = crcc57d_set_src, | ||
| .set_ctx = crcc37d_set_ctx, | ||
| .get_entry = crcc37d_get_entry, | ||
| .ctx_finished = crcc37d_ctx_finished, | ||
| .flip_threshold = CRCC37D_FLIP_THRESHOLD, | ||
| .num_entries = CRCC37D_MAX_ENTRIES, | ||
| .notifier_len = sizeof(struct crcc37d_notifier), | ||
| }; |
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