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Merge tag 'spi-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git…
…/broonie/spi
Pull spi updates from Mark Brown:
"The SPI subsystem has also had quite a quiet release, though with a
fairly large set of per-driver changes and several new drivers. The
bulk of the changes are:
- lots and lots of cleanups and improvements for the fsl-espi driver
- new drivers for Broadcom MSPI/iProc/STB, Cavium ThunderX and
J-Core"
* tag 'spi-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (80 commits)
spi: sc18is602: Change gpiod_set_value to gpiod_set_value_cansleep
spi: pxa2xx: Fix build error because of missing header
spi: imx: fix error return code in spi_imx_probe()
spi: pxa2xx: Add support for GPIO descriptor chip selects
spi: imx: Gracefully handle NULL master->cs_gpios
spi: iproc-qspi: Add Broadcom iProc SoCs support
spi: fsl-espi: improve return value handling in fsl_espi_probe
spi: fsl-espi: simplify of_fsl_espi_probe
spi: fsl-espi: remove unused variable in fsl_espi_setup
spi: bcm-qspi: Fix error return code in bcm_qspi_probe()
spi: bcm-qspi: Fix return value check in bcm_qspi_probe()
spi: bcm-qspi: fix suspend/resume #ifdef
spi: bcm-qspi: don't include linux/mtd/cfi.h
spi: core: Use spi_sync_transfer() in spi_write()/spi_read()
spi: fsl-espi: improve and extend register bit definitions
spi: fsl-espi: align register access with other drivers
spi: fsl-espi: improve and simplify interrupt handler
spi: fsl-espi: simplify fsl_espi_setup_transfer
spi: imx: support loopback mode on imx35
spi: imx: set spi_bus_clk for mx1, mx31 and mx35
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Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt
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| Broadcom SPI controller | ||
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| The Broadcom SPI controller is a SPI master found on various SOCs, including | ||
| BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits | ||
| of : | ||
| MSPI : SPI master controller can read and write to a SPI slave device | ||
| BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration | ||
| for flash reads and be configured to do single, double, quad lane | ||
| io with 3-byte and 4-byte addressing support. | ||
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| Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP. | ||
| MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance | ||
| of a MSPI master without the BSPI to use with non flash slave devices that | ||
| use SPI protocol. | ||
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| Required properties: | ||
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| - #address-cells: | ||
| Must be <1>, as required by generic SPI binding. | ||
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| - #size-cells: | ||
| Must be <0>, also as required by generic SPI binding. | ||
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| - compatible: | ||
| Must be one of : | ||
| "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs | ||
| "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI | ||
| BRCMSTB SoCs | ||
| "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : MSPI+BSPI on Cygnus, NSP | ||
| "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi" : NS2 SoCs | ||
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| - reg: | ||
| Define the bases and ranges of the associated I/O address spaces. | ||
| The required range is MSPI controller registers. | ||
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| - reg-names: | ||
| First name does not matter, but must be reserved for the MSPI controller | ||
| register range as mentioned in 'reg' above, and will typically contain | ||
| - "bspi_regs": BSPI register range, not required with compatible | ||
| "spi-brcmstb-mspi" | ||
| - "mspi_regs": MSPI register range is required for compatible strings | ||
| - "intr_regs", "intr_status_reg" : Interrupt and status register for | ||
| NSP, NS2, Cygnus SoC | ||
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| - interrupts | ||
| The interrupts used by the MSPI and/or BSPI controller. | ||
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| - interrupt-names: | ||
| Names of interrupts associated with MSPI | ||
| - "mspi_halted" : | ||
| - "mspi_done": Indicates that the requested SPI operation is complete. | ||
| - "spi_lr_fullness_reached" : Linear read BSPI pipe full | ||
| - "spi_lr_session_aborted" : Linear read BSPI pipe aborted | ||
| - "spi_lr_impatient" : Linear read BSPI requested when pipe empty | ||
| - "spi_lr_session_done" : Linear read BSPI session done | ||
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| - clocks: | ||
| A phandle to the reference clock for this block. | ||
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| Optional properties: | ||
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| - native-endian | ||
| Defined when using BE SoC and device uses BE register read/write | ||
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| Recommended optional m25p80 properties: | ||
| - spi-rx-bus-width: Definition as per | ||
| Documentation/devicetree/bindings/spi/spi-bus.txt | ||
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| Examples: | ||
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| BRCMSTB SoC Example: | ||
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| SPI Master (MSPI+BSPI) for SPI-NOR access: | ||
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| spi@f03e3400 { | ||
| #address-cells = <0x1>; | ||
| #size-cells = <0x0>; | ||
| compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-qspi"; | ||
| reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>; | ||
| reg-names = "cs_reg", "mspi", "bspi"; | ||
| interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>; | ||
| interrupt-parent = <0x1c>; | ||
| interrupt-names = "mspi_halted", | ||
| "mspi_done", | ||
| "spi_lr_overread", | ||
| "spi_lr_session_done", | ||
| "spi_lr_impatient", | ||
| "spi_lr_session_aborted", | ||
| "spi_lr_fullness_reached"; | ||
|
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| clocks = <&hif_spi>; | ||
| clock-names = "sw_spi"; | ||
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| m25p80@0 { | ||
| #size-cells = <0x2>; | ||
| #address-cells = <0x2>; | ||
| compatible = "m25p80"; | ||
| reg = <0x0>; | ||
| spi-max-frequency = <0x2625a00>; | ||
| spi-cpol; | ||
| spi-cpha; | ||
| m25p,fast-read; | ||
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| flash0.bolt@0 { | ||
| reg = <0x0 0x0 0x0 0x100000>; | ||
| }; | ||
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| flash0.macadr@100000 { | ||
| reg = <0x0 0x100000 0x0 0x10000>; | ||
| }; | ||
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| flash0.nvram@110000 { | ||
| reg = <0x0 0x110000 0x0 0x10000>; | ||
| }; | ||
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| flash0.kernel@120000 { | ||
| reg = <0x0 0x120000 0x0 0x400000>; | ||
| }; | ||
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| flash0.devtree@520000 { | ||
| reg = <0x0 0x520000 0x0 0x10000>; | ||
| }; | ||
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| flash0.splash@530000 { | ||
| reg = <0x0 0x530000 0x0 0x80000>; | ||
| }; | ||
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| flash0@0 { | ||
| reg = <0x0 0x0 0x0 0x4000000>; | ||
| }; | ||
| }; | ||
| }; | ||
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| MSPI master for any SPI device : | ||
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| spi@f0416000 { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| clocks = <&upg_fixed>; | ||
| compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-mspi"; | ||
| reg = <0xf0416000 0x180>; | ||
| reg-names = "mspi"; | ||
| interrupts = <0x14>; | ||
| interrupt-parent = <&irq0_aon_intc>; | ||
| interrupt-names = "mspi_done"; | ||
| }; | ||
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| iProc SoC Example: | ||
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| qspi: spi@18027200 { | ||
| compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; | ||
| reg = <0x18027200 0x184>, | ||
| <0x18027000 0x124>, | ||
| <0x1811c408 0x004>, | ||
| <0x180273a0 0x01c>; | ||
| reg-names = "mspi_regs", "bspi_regs", "intr_regs", "intr_status_reg"; | ||
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | ||
| <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, | ||
| <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, | ||
| <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, | ||
| <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, | ||
| <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, | ||
| <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | ||
| interrupt-names = | ||
| "spi_lr_fullness_reached", | ||
| "spi_lr_session_aborted", | ||
| "spi_lr_impatient", | ||
| "spi_lr_session_done", | ||
| "mspi_done", | ||
| "mspi_halted"; | ||
| clocks = <&iprocmed>; | ||
| clock-names = "iprocmed"; | ||
| num-cs = <2>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| }; | ||
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| NS2 SoC Example: | ||
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| qspi: spi@66470200 { | ||
| compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"; | ||
| reg = <0x66470200 0x184>, | ||
| <0x66470000 0x124>, | ||
| <0x67017408 0x004>, | ||
| <0x664703a0 0x01c>; | ||
| reg-names = "mspi", "bspi", "intr_regs", | ||
| "intr_status_reg"; | ||
| interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; | ||
| interrupt-names = "spi_l1_intr"; | ||
| clocks = <&iprocmed>; | ||
| clock-names = "iprocmed"; | ||
| num-cs = <2>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| }; | ||
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| m25p80 node for NSP, NS2 | ||
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| &qspi { | ||
| flash: m25p80@0 { | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| compatible = "m25p80"; | ||
| reg = <0x0>; | ||
| spi-max-frequency = <12500000>; | ||
| m25p,fast-read; | ||
| spi-cpol; | ||
| spi-cpha; | ||
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| partition@0 { | ||
| label = "boot"; | ||
| reg = <0x00000000 0x000a0000>; | ||
| }; | ||
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| partition@a0000 { | ||
| label = "env"; | ||
| reg = <0x000a0000 0x00060000>; | ||
| }; | ||
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| partition@100000 { | ||
| label = "system"; | ||
| reg = <0x00100000 0x00600000>; | ||
| }; | ||
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| partition@700000 { | ||
| label = "rootfs"; | ||
| reg = <0x00700000 0x01900000>; | ||
| }; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,34 @@ | ||
| J-Core SPI master | ||
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| Required properties: | ||
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| - compatible: Must be "jcore,spi2". | ||
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| - reg: Memory region for registers. | ||
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| - #address-cells: Must be 1. | ||
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| - #size-cells: Must be 0. | ||
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| Optional properties: | ||
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| - clocks: If a phandle named "ref_clk" is present, SPI clock speed | ||
| programming is relative to the frequency of the indicated clock. | ||
| Necessary only if the input clock rate is something other than a | ||
| fixed 50 MHz. | ||
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| - clock-names: Clock names, one for each phandle in clocks. | ||
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| See spi-bus.txt for additional properties not specific to this device. | ||
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| Example: | ||
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| spi@40 { | ||
| compatible = "jcore,spi2"; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| reg = <0x40 0x8>; | ||
| spi-max-frequency = <25000000>; | ||
| clocks = <&bus_clk>; | ||
| clock-names = "ref_clk"; | ||
| } |
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