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KVM: arm/arm64: vgic-new: Add GICv3 world switch backend
As the GICv3 virtual interface registers differ from their GICv2 siblings, we need different handlers for processing maintenance interrupts and reading/writing to the LRs. Implement the respective handler functions and connect them to existing code to be called if the host is using a GICv3. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
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Marc Zyngier
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Christoffer Dall
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May 20, 2016
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| /* | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| * | ||
| * This program is distributed in the hope that it will be useful, | ||
| * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| * GNU General Public License for more details. | ||
| * | ||
| * You should have received a copy of the GNU General Public License | ||
| * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
| */ | ||
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| #include <linux/irqchip/arm-gic-v3.h> | ||
| #include <linux/kvm.h> | ||
| #include <linux/kvm_host.h> | ||
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| #include "vgic.h" | ||
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| void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu) | ||
| { | ||
| struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; | ||
| u32 model = vcpu->kvm->arch.vgic.vgic_model; | ||
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| if (cpuif->vgic_misr & ICH_MISR_EOI) { | ||
| unsigned long eisr_bmap = cpuif->vgic_eisr; | ||
| int lr; | ||
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| for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) { | ||
| u32 intid; | ||
| u64 val = cpuif->vgic_lr[lr]; | ||
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| if (model == KVM_DEV_TYPE_ARM_VGIC_V3) | ||
| intid = val & ICH_LR_VIRTUAL_ID_MASK; | ||
| else | ||
| intid = val & GICH_LR_VIRTUALID; | ||
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| WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE); | ||
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| kvm_notify_acked_irq(vcpu->kvm, 0, | ||
| intid - VGIC_NR_PRIVATE_IRQS); | ||
| } | ||
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| /* | ||
| * In the next iterations of the vcpu loop, if we sync | ||
| * the vgic state after flushing it, but before | ||
| * entering the guest (this happens for pending | ||
| * signals and vmid rollovers), then make sure we | ||
| * don't pick up any old maintenance interrupts here. | ||
| */ | ||
| cpuif->vgic_eisr = 0; | ||
| } | ||
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| cpuif->vgic_hcr &= ~ICH_HCR_UIE; | ||
| } | ||
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| void vgic_v3_set_underflow(struct kvm_vcpu *vcpu) | ||
| { | ||
| struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; | ||
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| cpuif->vgic_hcr |= ICH_HCR_UIE; | ||
| } | ||
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| void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) | ||
| { | ||
| struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; | ||
| u32 model = vcpu->kvm->arch.vgic.vgic_model; | ||
| int lr; | ||
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| for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) { | ||
| u64 val = cpuif->vgic_lr[lr]; | ||
| u32 intid; | ||
| struct vgic_irq *irq; | ||
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| if (model == KVM_DEV_TYPE_ARM_VGIC_V3) | ||
| intid = val & ICH_LR_VIRTUAL_ID_MASK; | ||
| else | ||
| intid = val & GICH_LR_VIRTUALID; | ||
| irq = vgic_get_irq(vcpu->kvm, vcpu, intid); | ||
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| spin_lock(&irq->irq_lock); | ||
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| /* Always preserve the active bit */ | ||
| irq->active = !!(val & ICH_LR_ACTIVE_BIT); | ||
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| /* Edge is the only case where we preserve the pending bit */ | ||
| if (irq->config == VGIC_CONFIG_EDGE && | ||
| (val & ICH_LR_PENDING_BIT)) { | ||
| irq->pending = true; | ||
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| if (vgic_irq_is_sgi(intid) && | ||
| model == KVM_DEV_TYPE_ARM_VGIC_V2) { | ||
| u32 cpuid = val & GICH_LR_PHYSID_CPUID; | ||
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| cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT; | ||
| irq->source |= (1 << cpuid); | ||
| } | ||
| } | ||
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| /* Clear soft pending state when level irqs have been acked */ | ||
| if (irq->config == VGIC_CONFIG_LEVEL && | ||
| !(val & ICH_LR_PENDING_BIT)) { | ||
| irq->soft_pending = false; | ||
| irq->pending = irq->line_level; | ||
| } | ||
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| spin_unlock(&irq->irq_lock); | ||
| } | ||
| } | ||
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| /* Requires the irq to be locked already */ | ||
| void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr) | ||
| { | ||
| u32 model = vcpu->kvm->arch.vgic.vgic_model; | ||
| u64 val = irq->intid; | ||
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| if (irq->pending) { | ||
| val |= ICH_LR_PENDING_BIT; | ||
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| if (irq->config == VGIC_CONFIG_EDGE) | ||
| irq->pending = false; | ||
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| if (vgic_irq_is_sgi(irq->intid) && | ||
| model == KVM_DEV_TYPE_ARM_VGIC_V2) { | ||
| u32 src = ffs(irq->source); | ||
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| BUG_ON(!src); | ||
| val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT; | ||
| irq->source &= ~(1 << (src - 1)); | ||
| if (irq->source) | ||
| irq->pending = true; | ||
| } | ||
| } | ||
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| if (irq->active) | ||
| val |= ICH_LR_ACTIVE_BIT; | ||
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| if (irq->hw) { | ||
| val |= ICH_LR_HW; | ||
| val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT; | ||
| } else { | ||
| if (irq->config == VGIC_CONFIG_LEVEL) | ||
| val |= ICH_LR_EOI; | ||
| } | ||
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| /* | ||
| * We currently only support Group1 interrupts, which is a | ||
| * known defect. This needs to be addressed at some point. | ||
| */ | ||
| if (model == KVM_DEV_TYPE_ARM_VGIC_V3) | ||
| val |= ICH_LR_GROUP; | ||
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| val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT; | ||
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| vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val; | ||
| } | ||
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| void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr) | ||
| { | ||
| vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0; | ||
| } |
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