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drm/amd: Add DCN401 related register definitions
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Update register headers.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Aurabindo Pillai authored and Alex Deucher committed Apr 26, 2024
1 parent 96557f7 commit 59a0c03
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Showing 9 changed files with 162,669 additions and 0 deletions.
108 changes: 108 additions & 0 deletions drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
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Original file line number Diff line number Diff line change
Expand Up @@ -12855,6 +12855,24 @@
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0 0x3036
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1 0x3037
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2 0x3038
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3 0x3039
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a
#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_DATA0 0x303b
#define mmDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_DATA1 0x303c
#define mmDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_DATA2 0x303d
#define mmDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_DATA3 0x303e
#define mmDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2


// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
Expand Down Expand Up @@ -12985,6 +13003,24 @@
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0 0x3092
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1 0x3093
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2 0x3094
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3 0x3095
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096
#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_DATA0 0x3097
#define mmDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_DATA1 0x3098
#define mmDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_DATA2 0x3099
#define mmDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_DATA3 0x309a
#define mmDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2


// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
Expand Down Expand Up @@ -13115,6 +13151,24 @@
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX0 0x30ee
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX1 0x30ef
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX2 0x30f0
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX3 0x30f1
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2
#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_DATA0 0x30f3
#define mmDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_DATA1 0x30f4
#define mmDSCC2_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_DATA2 0x30f5
#define mmDSCC2_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_DATA3 0x30f6
#define mmDSCC2_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2


// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
Expand Down Expand Up @@ -13245,6 +13299,24 @@
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX0 0x314a
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX1 0x314b
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX2 0x314c
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX3 0x314d
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x314e
#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_DATA0 0x314f
#define mmDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_DATA1 0x3150
#define mmDSCC3_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_DATA2 0x3151
#define mmDSCC3_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_DATA3 0x3152
#define mmDSCC3_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2


// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
Expand Down Expand Up @@ -13375,6 +13447,24 @@
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x31a5
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX0 0x31a6
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX1 0x31a7
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX2 0x31a8
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX3 0x31a9
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE 0x31aa
#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_DATA0 0x31ab
#define mmDSCC4_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_DATA1 0x31ac
#define mmDSCC4_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_DATA2 0x31ad
#define mmDSCC4_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_DATA3 0x31ae
#define mmDSCC4_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2


// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
Expand Down Expand Up @@ -13504,6 +13594,24 @@
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3201
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX0 0x3202
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX1 0x3203
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX2 0x3204
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX3 0x3205
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE 0x3206
#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_DATA0 0x3207
#define mmDSCC5_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_DATA1 0x3208
#define mmDSCC5_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_DATA2 0x3209
#define mmDSCC5_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_DATA3 0x320a
#define mmDSCC5_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2


// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
Expand Down
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