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Merge branch 'add-ethtool-ntuple-filters-support'
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Naveen Mamindlapalli says:

====================
Add ethtool ntuple filters support

This patch series adds support for ethtool ntuple filters, unicast
address filtering, VLAN offload and SR-IOV ndo handlers. All of the
above features are based on the Admin Function(AF) driver support to
install and delete the low level MCAM entries. Each MCAM entry is
programmed with the packet fields to match and what actions to take
if the match succeeds. The PF driver requests AF driver to allocate
set of MCAM entries to be used to install the flows by that PF. The
entries will be freed when the PF driver is unloaded.

* The patches 1 to 4 adds AF driver infrastructure to install and
  delete the low level MCAM flow entries.
* Patch 5 adds ethtool ntuple filter support.
* Patch 6 adds unicast MAC address filtering.
* Patch 7 adds support for dumping the MCAM entries via debugfs.
* Patches 8 to 10 adds support for VLAN offload.
* Patch 10 to 11 adds support for SR-IOV ndo handlers.
* Patch 12 adds support to read the MCAM entries.

Misc:
* Removed redundant mailbox NIX_RXVLAN_ALLOC.
====================

Link: https://lore.kernel.org/r/20201114195303.25967-1-naveenm@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Jakub Kicinski committed Nov 17, 2020
2 parents f736591 + 5a57966 commit 5cfa9a6
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Showing 20 changed files with 3,909 additions and 169 deletions.
2 changes: 1 addition & 1 deletion drivers/net/ethernet/marvell/octeontx2/af/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -9,4 +9,4 @@ obj-$(CONFIG_OCTEONTX2_AF) += octeontx2_af.o

octeontx2_mbox-y := mbox.o rvu_trace.o
octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \
rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o
rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o
2 changes: 2 additions & 0 deletions drivers/net/ethernet/marvell/octeontx2/af/common.h
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Original file line number Diff line number Diff line change
Expand Up @@ -162,6 +162,8 @@ enum nix_scheduler {
#define NIX_RX_ACTIONOP_UCAST_IPSEC (0x2ull)
#define NIX_RX_ACTIONOP_MCAST (0x3ull)
#define NIX_RX_ACTIONOP_RSS (0x4ull)
/* Use the RX action set in the default unicast entry */
#define NIX_RX_ACTION_DEFAULT (0xfull)

/* NIX TX action operation*/
#define NIX_TX_ACTIONOP_DROP (0x0ull)
Expand Down
170 changes: 159 additions & 11 deletions drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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Original file line number Diff line number Diff line change
Expand Up @@ -188,10 +188,19 @@ M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
npc_mcam_alloc_and_write_entry_rsp) \
M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
msg_req, npc_get_kex_cfg_rsp) \
M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
npc_install_flow_req, npc_install_flow_rsp) \
M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
npc_delete_flow_req, msg_rsp) \
M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
npc_mcam_read_entry_req, \
npc_mcam_read_entry_rsp) \
M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
msg_req, npc_mcam_read_base_rule_rsp) \
/* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
nix_lf_alloc_req, nix_lf_alloc_rsp) \
M(NIX_LF_FREE, 0x8001, nix_lf_free, msg_req, msg_rsp) \
M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
hwctx_disable_req, msg_rsp) \
Expand All @@ -200,7 +209,8 @@ M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \
M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
nix_vtag_config_rsp) \
M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
nix_rss_flowkey_cfg, \
nix_rss_flowkey_cfg_rsp) \
Expand All @@ -216,7 +226,6 @@ M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
nix_lso_format_cfg, \
nix_lso_format_cfg_rsp) \
M(NIX_RXVLAN_ALLOC, 0x8012, nix_rxvlan_alloc, msg_req, msg_rsp) \
M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
Expand Down Expand Up @@ -473,6 +482,20 @@ enum nix_af_status {
NIX_AF_ERR_LSO_CFG_FAIL = -418,
NIX_AF_INVAL_NPA_PF_FUNC = -419,
NIX_AF_INVAL_SSO_PF_FUNC = -420,
NIX_AF_ERR_TX_VTAG_NOSPC = -421,
NIX_AF_ERR_RX_VTAG_INUSE = -422,
};

/* For NIX RX vtag action */
enum nix_rx_vtag0_type {
NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
NIX_AF_LFX_RX_VTAG_TYPE1,
NIX_AF_LFX_RX_VTAG_TYPE2,
NIX_AF_LFX_RX_VTAG_TYPE3,
NIX_AF_LFX_RX_VTAG_TYPE4,
NIX_AF_LFX_RX_VTAG_TYPE5,
NIX_AF_LFX_RX_VTAG_TYPE6,
NIX_AF_LFX_RX_VTAG_TYPE7,
};

/* For NIX LF context alloc and init */
Expand Down Expand Up @@ -510,6 +533,13 @@ struct nix_lf_alloc_rsp {
u8 sdp_links; /* No. of SDP links present in HW */
};

struct nix_lf_free_req {
struct mbox_msghdr hdr;
#define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
#define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
u64 flags;
};

/* NIX AQ enqueue msg */
struct nix_aq_enq_req {
struct mbox_msghdr hdr;
Expand Down Expand Up @@ -600,14 +630,40 @@ struct nix_vtag_config {
union {
/* valid when cfg_type is '0' */
struct {
/* tx vlan0 tag(C-VLAN) */
u64 vlan0;
/* tx vlan1 tag(S-VLAN) */
u64 vlan1;
/* insert tx vlan tag */
u8 insert_vlan :1;
/* insert tx double vlan tag */
u8 double_vlan :1;
u64 vtag0;
u64 vtag1;

/* cfg_vtag0 & cfg_vtag1 fields are valid
* when free_vtag0 & free_vtag1 are '0's.
*/
/* cfg_vtag0 = 1 to configure vtag0 */
u8 cfg_vtag0 :1;
/* cfg_vtag1 = 1 to configure vtag1 */
u8 cfg_vtag1 :1;

/* vtag0_idx & vtag1_idx are only valid when
* both cfg_vtag0 & cfg_vtag1 are '0's,
* these fields are used along with free_vtag0
* & free_vtag1 to free the nix lf's tx_vlan
* configuration.
*
* Denotes the indices of tx_vtag def registers
* that needs to be cleared and freed.
*/
int vtag0_idx;
int vtag1_idx;

/* free_vtag0 & free_vtag1 fields are valid
* when cfg_vtag0 & cfg_vtag1 are '0's.
*/
/* free_vtag0 = 1 clears vtag0 configuration
* vtag0_idx denotes the index to be cleared.
*/
u8 free_vtag0 :1;
/* free_vtag1 = 1 clears vtag1 configuration
* vtag1_idx denotes the index to be cleared.
*/
u8 free_vtag1 :1;
} tx;

/* valid when cfg_type is '1' */
Expand All @@ -622,6 +678,17 @@ struct nix_vtag_config {
};
};

struct nix_vtag_config_rsp {
struct mbox_msghdr hdr;
int vtag0_idx;
int vtag1_idx;
/* Indices of tx_vtag def registers used to configure
* tx vtag0 & vtag1 headers, these indices are valid
* when nix_vtag_config mbox requested for vtag0 and/
* or vtag1 configuration.
*/
};

struct nix_rss_flowkey_cfg {
struct mbox_msghdr hdr;
int mcam_index; /* MCAM entry index to modify */
Expand Down Expand Up @@ -882,6 +949,87 @@ struct npc_get_kex_cfg_rsp {
u8 mkex_pfl_name[MKEX_NAME_LEN];
};

struct flow_msg {
unsigned char dmac[6];
unsigned char smac[6];
__be16 etype;
__be16 vlan_etype;
__be16 vlan_tci;
union {
__be32 ip4src;
__be32 ip6src[4];
};
union {
__be32 ip4dst;
__be32 ip6dst[4];
};
u8 tos;
u8 ip_ver;
u8 ip_proto;
u8 tc;
__be16 sport;
__be16 dport;
};

struct npc_install_flow_req {
struct mbox_msghdr hdr;
struct flow_msg packet;
struct flow_msg mask;
u64 features;
u16 entry;
u16 channel;
u8 intf;
u8 set_cntr; /* If counter is available set counter for this entry ? */
u8 default_rule;
u8 append; /* overwrite(0) or append(1) flow to default rule? */
u16 vf;
/* action */
u32 index;
u16 match_id;
u8 flow_key_alg;
u8 op;
/* vtag rx action */
u8 vtag0_type;
u8 vtag0_valid;
u8 vtag1_type;
u8 vtag1_valid;
/* vtag tx action */
u16 vtag0_def;
u8 vtag0_op;
u16 vtag1_def;
u8 vtag1_op;
};

struct npc_install_flow_rsp {
struct mbox_msghdr hdr;
int counter; /* negative if no counter else counter number */
};

struct npc_delete_flow_req {
struct mbox_msghdr hdr;
u16 entry;
u16 start;/*Disable range of entries */
u16 end;
u8 all; /* PF + VFs */
};

struct npc_mcam_read_entry_req {
struct mbox_msghdr hdr;
u16 entry; /* MCAM entry to read */
};

struct npc_mcam_read_entry_rsp {
struct mbox_msghdr hdr;
struct mcam_entry entry_data;
u8 intf;
u8 enable;
};

struct npc_mcam_read_base_rule_rsp {
struct mbox_msghdr hdr;
struct mcam_entry entry;
};

enum ptp_op {
PTP_OP_ADJFINE = 0,
PTP_OP_GET_CLOCK = 1,
Expand Down
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