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drm/amd/powerplay: Enable ACG SS feature
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Port the atomfirmware.h and populates the
updated pptable to SMU.With the new parameters
in the new pptable, the ACG SS feature is enabled.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Kenneth Feng authored and Alex Deucher committed Apr 3, 2018
1 parent 4a8e06f commit 5d41535
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Showing 5 changed files with 39 additions and 18 deletions.
12 changes: 8 additions & 4 deletions drivers/gpu/drm/amd/include/atomfirmware.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1264,9 +1264,9 @@ struct atom_smc_dpm_info_v4_1
uint8_t ledpin2;
uint8_t padding8_4;

uint8_t gfxclkspreadenabled;
uint8_t gfxclkspreadpercent;
uint16_t gfxclkspreadfreq;
uint8_t pllgfxclkspreadenabled;
uint8_t pllgfxclkspreadpercent;
uint16_t pllgfxclkspreadfreq;

uint8_t uclkspreadenabled;
uint8_t uclkspreadpercent;
Expand All @@ -1276,7 +1276,11 @@ struct atom_smc_dpm_info_v4_1
uint8_t socclkspreadpercent;
uint16_t socclkspreadfreq;

uint32_t boardreserved[3];
uint8_t acggfxclkspreadenabled;
uint8_t acggfxclkspreadpercent;
uint16_t acggfxclkspreadfreq;

uint32_t boardreserved[10];
};


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10 changes: 7 additions & 3 deletions drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
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Original file line number Diff line number Diff line change
Expand Up @@ -616,9 +616,9 @@ int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
param->ledpin1 = info->ledpin1;
param->ledpin2 = info->ledpin2;

param->gfxclkspreadenabled = info->gfxclkspreadenabled;
param->gfxclkspreadpercent = info->gfxclkspreadpercent;
param->gfxclkspreadfreq = info->gfxclkspreadfreq;
param->pllgfxclkspreadenabled = info->pllgfxclkspreadenabled;
param->pllgfxclkspreadpercent = info->pllgfxclkspreadpercent;
param->pllgfxclkspreadfreq = info->pllgfxclkspreadfreq;

param->uclkspreadenabled = info->uclkspreadenabled;
param->uclkspreadpercent = info->uclkspreadpercent;
Expand All @@ -628,5 +628,9 @@ int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
param->socclkspreadpercent = info->socclkspreadpercent;
param->socclkspreadfreq = info->socclkspreadfreq;

param->acggfxclkspreadenabled = info->acggfxclkspreadenabled;
param->acggfxclkspreadpercent = info->acggfxclkspreadpercent;
param->acggfxclkspreadfreq = info->acggfxclkspreadfreq;

return 0;
}
10 changes: 7 additions & 3 deletions drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
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Original file line number Diff line number Diff line change
Expand Up @@ -192,9 +192,9 @@ struct pp_atomfwctrl_smc_dpm_parameters
uint8_t ledpin1;
uint8_t ledpin2;

uint8_t gfxclkspreadenabled;
uint8_t gfxclkspreadpercent;
uint16_t gfxclkspreadfreq;
uint8_t pllgfxclkspreadenabled;
uint8_t pllgfxclkspreadpercent;
uint16_t pllgfxclkspreadfreq;

uint8_t uclkspreadenabled;
uint8_t uclkspreadpercent;
Expand All @@ -203,6 +203,10 @@ struct pp_atomfwctrl_smc_dpm_parameters
uint8_t socclkspreadenabled;
uint8_t socclkspreadpercent;
uint16_t socclkspreadfreq;

uint8_t acggfxclkspreadenabled;
uint8_t acggfxclkspreadpercent;
uint16_t acggfxclkspreadfreq;
};

int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
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11 changes: 8 additions & 3 deletions drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
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Original file line number Diff line number Diff line change
Expand Up @@ -208,9 +208,9 @@ static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable
ppsmc_pptable->LedPin1 = smc_dpm_table.ledpin1;
ppsmc_pptable->LedPin2 = smc_dpm_table.ledpin2;

ppsmc_pptable->GfxclkSpreadEnabled = smc_dpm_table.gfxclkspreadenabled;
ppsmc_pptable->GfxclkSpreadPercent = smc_dpm_table.gfxclkspreadpercent;
ppsmc_pptable->GfxclkSpreadFreq = smc_dpm_table.gfxclkspreadfreq;
ppsmc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table.pllgfxclkspreadenabled;
ppsmc_pptable->PllGfxclkSpreadPercent = smc_dpm_table.pllgfxclkspreadpercent;
ppsmc_pptable->PllGfxclkSpreadFreq = smc_dpm_table.pllgfxclkspreadfreq;

ppsmc_pptable->UclkSpreadEnabled = 0;
ppsmc_pptable->UclkSpreadPercent = smc_dpm_table.uclkspreadpercent;
Expand All @@ -220,6 +220,11 @@ static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable
ppsmc_pptable->SocclkSpreadPercent = smc_dpm_table.socclkspreadpercent;
ppsmc_pptable->SocclkSpreadFreq = smc_dpm_table.socclkspreadfreq;

ppsmc_pptable->AcgGfxclkSpreadEnabled = smc_dpm_table.acggfxclkspreadenabled;
ppsmc_pptable->AcgGfxclkSpreadPercent = smc_dpm_table.acggfxclkspreadpercent;
ppsmc_pptable->AcgGfxclkSpreadFreq = smc_dpm_table.acggfxclkspreadfreq;


return 0;
}

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14 changes: 9 additions & 5 deletions drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h
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Original file line number Diff line number Diff line change
Expand Up @@ -127,7 +127,7 @@
#define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT )
#define FEATURE_GFXOFF_MASK (1 << FEATURE_GFXOFF_BIT )
#define FEATURE_CG_MASK (1 << FEATURE_CG_BIT )
#define FEATURE_ACG_MASK (1 << FEATURE_ACG_BIT )
#define FEATURE_ACG_MASK (1 << FEATURE_ACG_BIT)
#define FEATURE_SPARE_29_MASK (1 << FEATURE_SPARE_29_BIT )
#define FEATURE_SPARE_30_MASK (1 << FEATURE_SPARE_30_BIT )
#define FEATURE_SPARE_31_MASK (1 << FEATURE_SPARE_31_BIT )
Expand Down Expand Up @@ -481,9 +481,9 @@ typedef struct {
uint8_t padding8_4;


uint8_t GfxclkSpreadEnabled;
uint8_t GfxclkSpreadPercent;
uint16_t GfxclkSpreadFreq;
uint8_t PllGfxclkSpreadEnabled;
uint8_t PllGfxclkSpreadPercent;
uint16_t PllGfxclkSpreadFreq;

uint8_t UclkSpreadEnabled;
uint8_t UclkSpreadPercent;
Expand All @@ -493,7 +493,11 @@ typedef struct {
uint8_t SocclkSpreadPercent;
uint16_t SocclkSpreadFreq;

uint32_t BoardReserved[3];
uint8_t AcgGfxclkSpreadEnabled;
uint8_t AcgGfxclkSpreadPercent;
uint16_t AcgGfxclkSpreadFreq;

uint32_t BoardReserved[10];


uint32_t MmHubPadding[7];
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