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ARM: S5P64X0: Move GPIO support files for merge S5P64X0
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This patch moves S5P6440 GPIO support files from mach-s5p6440
into the new mach-s5p64x0 for merge S5P6440 and S5P6450 SocS.
NOTE: Not supported S5P6450 GPIO yet. Will be supported soon.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Kukjin Kim committed Oct 18, 2010
1 parent 2853a0e commit 5dd33d8
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Showing 4 changed files with 208 additions and 138 deletions.
80 changes: 0 additions & 80 deletions arch/arm/mach-s5p6440/include/mach/gpio.h
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99 changes: 51 additions & 48 deletions arch/arm/mach-s5p6440/gpio.c → arch/arm/mach-s5p64x0/gpio.c
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Original file line number Diff line number Diff line change
@@ -1,14 +1,14 @@
/* arch/arm/mach-s5p6440/gpio.c
/* linux/arch/arm/mach-s5p64x0/gpio.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P6440 - GPIOlib support
* S5P64X0 - GPIOlib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
*/

#include <linux/kernel.h>
#include <linux/irq.h>
Expand All @@ -22,26 +22,29 @@
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>

/* GPIO bank summary:
*
* Bank GPIOs Style SlpCon ExtInt Group
* A 6 4Bit Yes 1
* B 7 4Bit Yes 1
* C 8 4Bit Yes 2
* F 2 2Bit Yes 4 [1]
* G 7 4Bit Yes 5
* H 10 4Bit[2] Yes 6
* I 16 2Bit Yes None
* J 12 2Bit Yes None
* N 16 2Bit No IRQ_EINT
* P 8 2Bit Yes 8
* R 15 4Bit[2] Yes 8
*
* [1] BANKF pins 14,15 do not form part of the external interrupt sources
* [2] BANK has two control registers, GPxCON0 and GPxCON1
*/
/* To be implemented S5P6450 GPIO */

/*
* S5P6440 GPIO bank summary:
*
* Bank GPIOs Style SlpCon ExtInt Group
* A 6 4Bit Yes 1
* B 7 4Bit Yes 1
* C 8 4Bit Yes 2
* F 2 2Bit Yes 4 [1]
* G 7 4Bit Yes 5
* H 10 4Bit[2] Yes 6
* I 16 2Bit Yes None
* J 12 2Bit Yes None
* N 16 2Bit No IRQ_EINT
* P 8 2Bit Yes 8
* R 15 4Bit[2] Yes 8
*
* [1] BANKF pins 14,15 do not form part of the external interrupt sources
* [2] BANK has two control registers, GPxCON0 and GPxCON1
*/

static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
unsigned int offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
Expand Down Expand Up @@ -77,7 +80,7 @@ static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
return 0;
}

static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
Expand Down Expand Up @@ -124,7 +127,7 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
return 0;
}

int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
Expand Down Expand Up @@ -167,14 +170,14 @@ int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
return 0;
}

static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
{
.cfg_eint = 0,
}, {
.cfg_eint = 7,
}, {
.cfg_eint = 3,
.set_config = s5p6440_gpio_setcfg_4bit_rbank,
.set_config = s5p64x0_gpio_setcfg_4bit_rbank,
}, {
.cfg_eint = 0,
.set_config = s3c_gpio_setcfg_s3c24xx,
Expand All @@ -193,31 +196,31 @@ static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
{
.base = S5P6440_GPA_BASE,
.config = &s5p6440_gpio_cfgs[1],
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPA(0),
.ngpio = S5P6440_GPIO_A_NR,
.label = "GPA",
},
}, {
.base = S5P6440_GPB_BASE,
.config = &s5p6440_gpio_cfgs[1],
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPB(0),
.ngpio = S5P6440_GPIO_B_NR,
.label = "GPB",
},
}, {
.base = S5P6440_GPC_BASE,
.config = &s5p6440_gpio_cfgs[1],
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPC(0),
.ngpio = S5P6440_GPIO_C_NR,
.label = "GPC",
},
}, {
.base = S5P6440_GPG_BASE,
.config = &s5p6440_gpio_cfgs[1],
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPG(0),
.ngpio = S5P6440_GPIO_G_NR,
Expand All @@ -229,7 +232,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
{
.base = S5P6440_GPH_BASE + 0x4,
.config = &s5p6440_gpio_cfgs[1],
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPH(0),
.ngpio = S5P6440_GPIO_H_NR,
Expand All @@ -238,10 +241,10 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
},
};

static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
{
.base = S5P6440_GPR_BASE + 0x4,
.config = &s5p6440_gpio_cfgs[2],
.config = &s5p64x0_gpio_cfgs[2],
.chip = {
.base = S5P6440_GPR(0),
.ngpio = S5P6440_GPIO_R_NR,
Expand All @@ -253,39 +256,39 @@ static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
{
.base = S5P6440_GPF_BASE,
.config = &s5p6440_gpio_cfgs[5],
.config = &s5p64x0_gpio_cfgs[5],
.chip = {
.base = S5P6440_GPF(0),
.ngpio = S5P6440_GPIO_F_NR,
.label = "GPF",
},
}, {
.base = S5P6440_GPI_BASE,
.config = &s5p6440_gpio_cfgs[3],
.config = &s5p64x0_gpio_cfgs[3],
.chip = {
.base = S5P6440_GPI(0),
.ngpio = S5P6440_GPIO_I_NR,
.label = "GPI",
},
}, {
.base = S5P6440_GPJ_BASE,
.config = &s5p6440_gpio_cfgs[3],
.config = &s5p64x0_gpio_cfgs[3],
.chip = {
.base = S5P6440_GPJ(0),
.ngpio = S5P6440_GPIO_J_NR,
.label = "GPJ",
},
}, {
.base = S5P6440_GPN_BASE,
.config = &s5p6440_gpio_cfgs[4],
.config = &s5p64x0_gpio_cfgs[4],
.chip = {
.base = S5P6440_GPN(0),
.ngpio = S5P6440_GPIO_N_NR,
.label = "GPN",
},
}, {
.base = S5P6440_GPP_BASE,
.config = &s5p6440_gpio_cfgs[5],
.config = &s5p64x0_gpio_cfgs[5],
.chip = {
.base = S5P6440_GPP(0),
.ngpio = S5P6440_GPIO_P_NR,
Expand All @@ -294,7 +297,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
},
};

void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
{
for (; nr_chips > 0; nr_chips--, chipcfg++) {
if (!chipcfg->set_config)
Expand All @@ -308,13 +311,13 @@ void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
}
}

static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
int nr_chips)
{
for (; nr_chips > 0; nr_chips--, chip++) {
chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input;
chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
chip->chip.direction_output =
s5p6440_gpiolib_rbank_4bit2_output;
s5p64x0_gpiolib_rbank_4bit2_output;
s3c_gpiolib_add(chip);
}
}
Expand All @@ -324,8 +327,8 @@ static int __init s5p6440_gpiolib_init(void)
struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);

s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs,
ARRAY_SIZE(s5p6440_gpio_cfgs));
s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
ARRAY_SIZE(s5p64x0_gpio_cfgs));

for (; nr_chips > 0; nr_chips--, chips++)
s3c_gpiolib_add(chips);
Expand All @@ -336,8 +339,8 @@ static int __init s5p6440_gpiolib_init(void)
samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
ARRAY_SIZE(s5p6440_gpio_4bit2));

s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2,
ARRAY_SIZE(gpio_rbank_4bit2));
s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));

return 0;
}
Expand Down
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