drm/nve0-/gr: some new gpc registers can have multiple copies

GK110 exposes more than one, and needs to be dealt with in the ctxsw ucode just like the TPC sets are. Broadcast is at +0xe00. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
mariux64 · Jul 5, 2013 · 5ee86c4 · 5ee86c4
1 parent c03ff9e
commit 5ee86c4
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Showing 4 changed files with 227 additions and 180 deletions.
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
@@ -38,6 +38,13 @@ tpc_mask:		.b32 0
 tpc_mmio_list_head:	.b32 0
 tpc_mmio_list_tail:	.b32 0
 
+#ifdef NVGK
+unk_count:		.b32 1
+unk_mask:		.b32 1
+unk_mmio_list_head:	.b32 #nve4_unk_mmio_head
+unk_mmio_list_tail:	.b32 #nve4_unk_mmio_tail
+#endif
+
 cmd_queue:		queue_init
 #endif
 
@@ -160,6 +167,17 @@ init:
 	add b32 $r2 $r14
 	add b32 $r3 $r14
 
+#ifdef NVGK
+	// calculate per-UNK mmio context size
+	ld b32 $r14 D[$r0 + #unk_mmio_list_head]
+	ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
+	call #mmctx_size
+	ld b32 $r14 D[$r0 + #unk_count]
+	mulu $r14 $r15
+	add b32 $r2 $r14
+	add b32 $r3 $r14
+#endif
+
 	// round up base/size to 256 byte boundary (for strand SWBASE)
 	add b32 $r4 0x1300
 	shr b32 $r3 2
@@ -335,7 +353,6 @@ ctx_xfer:
 
 	// per-TPC mmio context
 	xbit $r10 $flags $p1	// direction
-	or $r10 4		// last
 	mov $r11 0x4000
 	sethi $r11 0x500000	// base = NV_PGRAPH_GPC0_TPC0
 	ld b32 $r12 D[$r0 + #gpc_id]
@@ -347,6 +364,22 @@ ctx_xfer:
 	mov $r14 0x800		// stride = 0x800
 	call #mmctx_xfer
 
+#ifdef NVGK
+	// per-UNK mmio context
+	xbit $r10 $flags $p1	// direction
+	or $r10 4		// last
+	mov $r11 0x3000
+	sethi $r11 0x500000	// base = NV_PGRAPH_GPC0_UNK0
+	ld b32 $r12 D[$r0 + #gpc_id]
+	shl b32 $r12 15
+	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_UNK0
+	ld b32 $r12 D[$r0 + #unk_mmio_list_head]
+	ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
+	ld b32 $r15 D[$r0 + #unk_mask]
+	mov $r14 0x200		// stride = 0x200
+	call #mmctx_xfer
+#endif
+
 	// wait for strands to finish
 	call #strand_wait
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
@@ -496,26 +496,26 @@ uint32_t nvc0_grgpc_code[] = {
 	0xf0020d98,
 	0x21f500e7,
 	0xacf0015c,
-	0x04a5f001,
-	0x4000b7f1,
-	0x9850b3f0,
-	0xc4b6000c,
-	0x00bcbb0f,
-	0x98050c98,
-	0x0f98060d,
-	0x00e7f104,
-	0x5c21f508,
-	0x0721f501,
-	0x0601f402,
-/* 0x054b: ctx_xfer_post */
-	0xf11412f4,
-	0xf04afc17,
-	0x27f00213,
-	0x0012d00d,
-	0x020721f5,
-/* 0x055c: ctx_xfer_done */
-	0x048f21f5,
-	0x000000f8,
+	0x00b7f101,
+	0x50b3f040,
+	0xb6000c98,
+	0xbcbb0fc4,
+	0x050c9800,
+	0x98060d98,
+	0xe7f1040f,
+	0x21f50800,
+	0x21f5015c,
+	0x01f40207,
+	0x1412f406,
+/* 0x0548: ctx_xfer_post */
+	0x4afc17f1,
+	0xf00213f0,
+	0x12d00d27,
+	0x0721f500,
+/* 0x0559: ctx_xfer_done */
+	0x8f21f502,
+	0x0000f804,
+	0x00000000,
 	0x00000000,
 	0x00000000,
 	0x00000000,

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
@@ -82,12 +82,6 @@ mmctx_data(0x000c80, 1)
 mmctx_data(0x000c8c, 1)
 mmctx_data(0x001000, 3)
 mmctx_data(0x001014, 1)
-mmctx_data(0x003024, 1)
-mmctx_data(0x0030c0, 2)
-mmctx_data(0x0030e4, 1)
-mmctx_data(0x003100, 6)
-mmctx_data(0x0031d0, 1)
-mmctx_data(0x0031e0, 2)
 nve4_gpc_mmio_tail:
 
 nvf0_gpc_mmio_head:
@@ -166,6 +160,16 @@ mmctx_data(0x000758, 1)
 mmctx_data(0x000770, 1)
 mmctx_data(0x000778, 2)
 nvf0_tpc_mmio_tail:
+
+// UNK mmio lists
+nve4_unk_mmio_head:
+mmctx_data(0x000024, 1)
+mmctx_data(0x0000c0, 2)
+mmctx_data(0x0000e4, 1)
+mmctx_data(0x000100, 6)
+mmctx_data(0x0001d0, 1)
+mmctx_data(0x0001e0, 2)
+nve4_unk_mmio_tail:
 #undef INCLUDE_DATA
 
 .section #nve0_grgpc_code