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…benh/powerpc * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (158 commits) powerpc: Fix CHRP PCI config access for indirect_pci powerpc/chrp: Fix detection of Python PCI host bridge on IBM CHRPs powerpc: Fix 32-bit SMP boot on CHRP powerpc: Fix link errors on 32-bit machines using legacy DMA powerpc/pci: Improve detection of unassigned bridge resources hvc_console: Fix free_irq in spinlocked section powerpc: Get USE_STRICT_MM_TYPECHECKS working again powerpc: Reflect the used arguments in machine_init() prototype powerpc: Fix DMA offset for non-coherent DMA powerpc: fix fsl_upm nand driver modular build powerpc/83xx: add NAND support for the MPC8360E-RDK boards powerpc: FPGA support for GE Fanuc SBC610 i2c: MPC8349E-mITX Power Management and GPIO expander driver powerpc: reserve two DMA channels for audio in MPC8610 HPCD device tree powerpc: document the "fsl,ssi-dma-channel" compatible property powerpc: disable CHRP and PMAC support in various defconfigs OF: add fsl,mcu-mpc8349emitx to the exception list powerpc/83xx: add DS1374 RTC support for the MPC837xE-MDS boards powerpc: remove support for bootmem-allocated memory for the DIU driver powerpc: remove non-dependent load fsl_booke PTE_64BIT ...
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* Freescale 83xx and 512x PCI bridges | ||
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Freescale 83xx and 512x SOCs include the same pci bridge core. | ||
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83xx/512x specific notes: | ||
- reg: should contain two address length tuples | ||
The first is for the internal pci bridge registers | ||
The second is for the pci config space access registers | ||
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Example (MPC8313ERDB) | ||
pci0: pci@e0008500 { | ||
cell-index = <1>; | ||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
interrupt-map = < | ||
/* IDSEL 0x0E -mini PCI */ | ||
0x7000 0x0 0x0 0x1 &ipic 18 0x8 | ||
0x7000 0x0 0x0 0x2 &ipic 18 0x8 | ||
0x7000 0x0 0x0 0x3 &ipic 18 0x8 | ||
0x7000 0x0 0x0 0x4 &ipic 18 0x8 | ||
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/* IDSEL 0x0F - PCI slot */ | ||
0x7800 0x0 0x0 0x1 &ipic 17 0x8 | ||
0x7800 0x0 0x0 0x2 &ipic 18 0x8 | ||
0x7800 0x0 0x0 0x3 &ipic 17 0x8 | ||
0x7800 0x0 0x0 0x4 &ipic 18 0x8>; | ||
interrupt-parent = <&ipic>; | ||
interrupts = <66 0x8>; | ||
bus-range = <0x0 0x0>; | ||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 | ||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 | ||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; | ||
clock-frequency = <66666666>; | ||
#interrupt-cells = <1>; | ||
#size-cells = <2>; | ||
#address-cells = <3>; | ||
reg = <0xe0008500 0x100 /* internal registers */ | ||
0xe0008300 0x8>; /* config space access registers */ | ||
compatible = "fsl,mpc8349-pci"; | ||
device_type = "pci"; | ||
}; |
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GPIO controllers on MPC8xxx SoCs | ||
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This is for the non-QE/CPM/GUTs GPIO controllers as found on | ||
8349, 8572, 8610 and compatible. | ||
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Every GPIO controller node must have #gpio-cells property defined, | ||
this information will be used to translate gpio-specifiers. | ||
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Required properties: | ||
- compatible : "fsl,<CHIP>-gpio" followed by "fsl,mpc8349-gpio" for | ||
83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx. | ||
- #gpio-cells : Should be two. The first cell is the pin number and the | ||
second cell is used to specify optional parameters (currently unused). | ||
- interrupts : Interrupt mapping for GPIO IRQ (currently unused). | ||
- interrupt-parent : Phandle for the interrupt controller that | ||
services interrupts for this device. | ||
- gpio-controller : Marks the port as GPIO controller. | ||
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Example of gpio-controller nodes for a MPC8347 SoC: | ||
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gpio1: gpio-controller@c00 { | ||
#gpio-cells = <2>; | ||
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; | ||
reg = <0xc00 0x100>; | ||
interrupts = <74 0x8>; | ||
interrupt-parent = <&ipic>; | ||
gpio-controller; | ||
}; | ||
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gpio2: gpio-controller@d00 { | ||
#gpio-cells = <2>; | ||
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; | ||
reg = <0xd00 0x100>; | ||
interrupts = <75 0x8>; | ||
interrupt-parent = <&ipic>; | ||
gpio-controller; | ||
}; | ||
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See booting-without-of.txt for details of how to specify GPIO | ||
information for devices. |
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