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drm/amd/display: determine if a pipe is synced by plane state
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[why]
is_blanked is not a general indicator of if a pipe is synced
for all asics.
plane state is more accurate and applicable for all asics.

[how]
Remove is_blanked call and
add checking plane_state against NULL instead.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Wenjing Liu authored and Alex Deucher committed Feb 6, 2019
1 parent 8f01591 commit 5fc0cbf
Showing 1 changed file with 4 additions and 4 deletions.
8 changes: 4 additions & 4 deletions drivers/gpu/drm/amd/display/dc/core/dc.c
Original file line number Diff line number Diff line change
Expand Up @@ -907,11 +907,11 @@ static void program_timing_sync(
}
}

/* set first unblanked pipe as master */
/* set first pipe with plane as master */
for (j = 0; j < group_size; j++) {
struct pipe_ctx *temp;

if (pipe_set[j]->stream_res.tg->funcs->is_blanked && !pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) {
if (pipe_set[j]->plane_state) {
if (j == 0)
break;

Expand All @@ -922,9 +922,9 @@ static void program_timing_sync(
}
}

/* remove any other unblanked pipes as they have already been synced */
/* remove any other pipes with plane as they have already been synced */
for (j = j + 1; j < group_size; j++) {
if (pipe_set[j]->stream_res.tg->funcs->is_blanked && !pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) {
if (pipe_set[j]->plane_state) {
group_size--;
pipe_set[j] = pipe_set[group_size];
j--;
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